> ## Content Index > Fetch the complete content index at: https://www.sotkn.com/llms.txt > Use this file to discover other available public pages before exploring further. # What Is a Chiplet? Why AI Chips Are Now Built in Pieces - URL: https://www.sotkn.com/explained/chiplet-explained/ - Published: 2026-10-20T01:11:58.000Z - Updated: 2026-10-20T01:11:58.000Z - Description: A chiplet is a small die designed to be joined with other dies in one package. AI chips are now built this way because one die has hit its size limit. The foundry is paid for every piece; the packager is paid for the join, and the join is where supply is short. - Author: Sean - Tags: Mechanism, #desk-explained EXPLAINED · Mechanism · Last reviewed: 20 Oct 2026 · Next review: after TSMC's fourth-quarter 2026 earnings call in January 2027 A chiplet is a small chip die designed to be joined with other dies inside one package, so that together they work as a single processor. Instead of one large slab of silicon, the chip is built from pieces. **In short.** A chiplet is one piece of a processor that has been split into several dies and joined back together inside one package. AI chips are now built this way for three reasons: one die cannot be printed larger than about 858 square millimetres, small dies lose less silicon to defects, and each piece can use the cheapest process that does its job. Nvidia’s Blackwell joins two dies; AMD’s MI455X, launched in July 2026, joins 12 logic dies and 12 memory stacks. The foundry is paid for every piece. The packager is paid for the join, and the join is the stuck step: TSMC said on 15 October 2026 that demand is still far above what it can supply. Why an investor cares: when an AI chip is built from pieces, the money moves. The foundry sells more wafers, on more than one process, for every accelerator, and the packaging step that joins the pieces becomes a business, and a bottleneck, of its own. If the packaging terms are new, start with [how CoWoS works](https://www.sotkn.com/explained/cowos-explained/) and [what an interposer is](https://www.sotkn.com/explained/interposer-explained/). ## What is a chiplet? A chiplet is a die that is not meant to work alone. A die is the small rectangle of silicon cut from a wafer that carries a circuit. In a normal chip, one die holds the whole design. In a chiplet design, the design is split across several dies, each made and tested on its own, then placed together in one package and wired so closely that the system behaves like one chip. The package is the key word. The pieces sit side by side on a shared layer, or stacked on top of one another, and talk through short, dense links called die-to-die interconnects. Those links are what make several dies act as one. Without them, you would just have several chips on a board, talking slowly over long wires. The opposite of a chiplet design is a monolithic chip: one die, one process, everything in one place. For decades that was the goal, because putting more on one die made it faster and cheaper. AMD’s CDNA 4 white paper, published with its MI350 GPUs in June 2025, calls the shift away from that model a fundamental rethinking of silicon design. It describes AMD’s previous generation as “repartitioning a processor across a dozen different chiplets”. | | Monolithic chip | Chiplet design | | ---------------------------- | ---------------------------------------- | ----------------------------------------------------------------- | | **What it is** | The whole design on one piece of silicon | The design split across several dies joined inside one package | | **Size limit** | One reticle, about 26 × 33 mm | Several reticles; TSMC is in production at five times one reticle | | **A defect costs** | The whole large die | One small die, caught in test before assembly | | **Processes** | One process for everything | Each die on the process that suits it | | **Extra cost** | None for joining | Die-to-die links, packaging, and good dies lost when a join fails | | **Who gets the extra money** | The foundry, on one big die | The foundry on every die, plus the packager for the join | *Our summary. The size and production figures are TSMC’s; the cost rows follow the 2022 academic model listed under References.* ## Why are AI chips built from chiplets? Three reasons: the size wall, defects, and cost per process. The first is the one that forced Nvidia’s hand. The size wall is the reticle. A lithography tool prints a chip one field at a time, and the largest field it can print is about 26 by 33 millimetres, or 858 square millimetres. No single die can be bigger. Nvidia’s Hot Chips 2024 presentation shows how close its GPUs already sat to that line: Volta at 815 square millimetres, Ampere at 826 and Hopper at 814\. Hopper used about 95% of the field (our arithmetic: 814 ÷ 858). So Blackwell went to two dies. Nvidia describes it as two reticle-limited GPU dies, together more than 1,600 square millimetres, joined by a 10 TB/s link it calls NV-HBI, so that software sees “a single, unified GPU” with 208 billion transistors. Rubin, which Nvidia detailed on 21 July 2026, keeps the two-die design and lifts the count to 336 billion, about 62% more (our arithmetic). Our [EUV lithography explainer](https://www.sotkn.com/explained/euv-lithography-explained/) covers the tool that sets the field size. The second reason is defects. Every wafer carries a scattering of tiny flaws, and a flaw anywhere on a die can ruin it. The bigger the die, the more likely it catches one, so a giant die wastes more silicon per good chip. A peer-reviewed cost model presented at the Design Automation Conference in 2022 found that on a 5-nanometre process, defects make up more than half the manufacturing cost of an 800 square millimetre monolithic chip. Smaller dies catch fewer flaws, and a bad one can be thrown away before it is joined to anything. Chip designers also leave spare parts on each die. AMD’s MI355X compute dies each carry 36 compute units, of which 32 are switched on, leaving four that may be disabled “to enable high yield”, the company says. A die with a flaw in one unit can still be sold. The third reason is cost per process. Not every circuit gets faster or smaller on a newer process. AMD says the cache, memory controllers and links in its I/O dies “do not effectively scale” on the latest technology, so on the MI355X it kept them on TSMC’s older N6 process, which it calls “highly efficient and affordable”, while the compute dies moved to N3P. On the MI455X the compute dies moved again, to TSMC’s 2-nanometre N2, with the other dies on N3P. Each piece pays only for the process it needs. | AI chip | Logic dies | Processes | Memory | Transistors | | ------------------------------------- | ------------------------------------------------------------------- | ---------------------------- | ------------------------- | ----------- | | **Nvidia Blackwell** (2024) | 2 compute dies, each at the reticle limit, joined by a 10 TB/s link | TSMC 4NP | 8 HBM3e sites | 208 billion | | **Nvidia Rubin** (described Jul 2026) | 2 reticle-limited compute dies joined by NV-HBI | Not stated in the source | 288 GB of HBM4 | 336 billion | | **AMD MI355X** (Jun 2025) | 8 compute dies stacked on 2 I/O dies | Compute on N3P, I/O on N6 | 8 stacks of HBM3E | 185 billion | | **AMD MI455X** (launched 23 Jul 2026) | 8 compute, 2 I/O and 2 fabric-and-cache dies | Compute on N2, others on N3P | 12 stacks of HBM4, 432 GB | 320 billion | *As each company describes its own chip. Sources under References.* ## How do chiplets talk to each other? Through die-to-die links, and the package that carries them. The link sets how much data crosses between pieces; the package sets how many pieces fit and how close they sit. The big AI chips use their makers’ own links. Nvidia joins Blackwell’s two dies with NV-HBI at 10 TB/s across a single edge, and AMD ties its dies together with its Infinity Fabric. There is also an open standard, Universal Chiplet Interconnect Express, or UCIe. Its consortium formed in March 2022, and on 5 August 2025 it released version 3.0, which raises link speed to 48 and 64 GT/s, double the 32 GT/s of version 2.0\. Our read: an open standard matters most for companies that want to mix dies from different suppliers; the leading AI accelerators still use links their designers control. The pieces can sit side by side or on top of each other. Side by side, they share an [interposer](https://www.sotkn.com/explained/interposer-explained/), a thin sheet that carries the dense wiring between them, which is TSMC’s CoWoS. Stacked, one die is bonded straight onto another. AMD stacks the MI355X’s eight compute dies on top of its two I/O dies, and then sets that stack beside the memory. The stacking step is explained in [hybrid bonding](https://www.sotkn.com/explained/hybrid-bonding-explained/), and Intel’s bridge-based alternative to a full interposer in [CoWoS vs EMIB](https://www.sotkn.com/explained/cowos-vs-emib/). Memory is part of the count too. High-bandwidth memory, or [HBM](https://www.sotkn.com/explained/hbm-explained/), arrives as stacks of memory dies that sit beside the processor on the same package, and each stack has its own logic die at the bottom. AMD went from eight HBM3E stacks on the MI355X to 12 HBM4 stacks on the MI455X, 50% more (our arithmetic). Our [Wire on Nvidia’s custom HBM base dies](https://www.sotkn.com/wire/samsung-tsmc-3nm-nvhbm-base-die-nvidia-custom-hbm-wire/) covers a report that Nvidia wants that bottom die made on TSMC’s 3-nanometre process, which would make the memory stack one more TSMC logic chiplet. ![Chiplets: pieces on one AI package, from 10 on Nvidia Blackwell in 2024 to 18 on AMD MI355X, 24 on AMD MI455X in 2026 and 40 in TSMC's 2028 plan](https://storage.ghost.io/c/cd/10/cd10e222-131f-4ba4-b4a9-ca4214e8c12d/content/images/2026/10/chiplet-pieces-per-package.png) Logic dies plus memory stacks per package. Second Order count from Nvidia, AMD and TSMC figures; the 2028 bar is a plan. Count the pieces and the trend is plain. Blackwell carries two compute dies and eight memory sites, 10 pieces. The MI355X carries 10 logic dies and eight memory stacks, 18\. The MI455X carries 12 logic dies and 12 memory stacks, 24\. TSMC’s roadmap, as reported from its April 2026 symposium, has a 2028 package carrying 20 stacked compute chiplets and 20 HBM5 stacks, 40 pieces (our count). Every extra piece is another die to make, another die to test and another join to get right. ## Who gets paid when a chip is split into chiplets? The foundry first, the packager second, the memory and substrate makers alongside. The chip designer keeps the savings, if the joins work. The foundry is paid per wafer for every die, not per finished chip. On the MI455X that means compute dies on TSMC’s N2 and the other logic dies on N3P, so one accelerator draws on two of TSMC’s processes at once. TSMC said on 15 October 2026 that N2 entered volume production in the fourth quarter of 2025 and that its N2 capacity will more than double in 2027\. Our read: chiplets let a designer use the newest process for the compute dies, the part that most needs it, and that is where the most expensive wafers go. The packager is paid for the join. At TSMC this is its advanced packaging line, which places and bonds the dies, the interposer and the memory. TSMC’s symposium message in April 2026, as reported, was that “AI compute scaling is driven by the combination of advanced logic, SoIC 3D stacking, and CoWoS technologies”: in plain words, the newest process, stacking and side-by-side packaging, together. [Who makes advanced packaging](https://www.sotkn.com/explained/who-makes-advanced-packaging/) maps the firms that do this work. Memory and substrate makers are paid alongside. More pieces need more HBM stacks and a bigger base under the package. The 2027 package on TSMC’s roadmap needs a substrate 120 by 150 millimetres, as reported. [IC substrates and ABF](https://www.sotkn.com/explained/ic-substrates-abf-explained/) explains that layer and why it can bind on its own. The chip designer is paid in yield and flexibility. It buys smaller, cheaper-to-perfect dies, reuses them across products and swaps only the pieces that change. The 2022 cost model found that for AMD’s chiplet processors, splitting the design could save up to half of the die cost. Then it added the bill for joining them: in one 16-core example, packaging was about 30% of the total cost. ![Chiplets explained: how a chiplet AI chip gets built and paid, from the design split, the wafers and die testing to the join and the finished module](https://storage.ghost.io/c/cd/10/cd10e222-131f-4ba4-b4a9-ca4214e8c12d/content/images/2026/10/chiplet-how-it-gets-paid.png) Stuck step: the join. Second Order. ## Where is the stuck step? At the join. Splitting a chip makes each die easier to make and moves the hard part to putting the dies back together. That step has its own capacity, its own yield and its own cost. Capacity first. TSMC’s chief executive, C.C. Wei, said on the 15 October 2026 call that the company is in production at five times the reticle size, with excellent yield, and is working on nine times and then 14 times. On demand he said: “the demand actually is still far above our capability today to supply.” TSMC is building 13 leading-edge and advanced packaging fabs in Taiwan over the next several years, it said. Our read: the bigger the package, the more chiplets and memory stacks queue for each slot. Yield next. A die that tests good can still be lost if the join fails. The 2022 cost model calls these wasted known good dies, and found that in a large side-by-side package, its 7-nanometre, 900 square millimetre example, packaging including those losses was about half the total cost, comparable with the chips themselves. Our read: when one package carries 24 or 40 pieces, a single bad bond scraps more good silicon than it did when a package carried two. Cost last. The same model found the savings from cutting a chip into more and smaller pieces shrink quickly: going from three chiplets to five saved less than 10% more at 5 nanometres. Splitting is not free, and at some point each extra join costs more than it saves. TSMC said it is also working on a panel-based packaging method it calls CoPoS to bring a “reasonable cost reduction” in future, which tells you where the cost pressure sits. | When | Package size (multiples of one reticle) | What it carries | Status | | ------------ | ---------------------------------------------- | ------------------------------------------ | ------------------------------------------------------------ | | **2024** | About 2 (Blackwell’s two dies, over 1,600 mm²) | 2 compute dies, 8 HBM3e | Shipped | | **Oct 2026** | 5x | Today’s largest AI packages | In production with excellent yield, TSMC said on 15 Oct 2026 | | **2027** | 9.5x | 12 HBM5 stacks on a 120 × 150 mm substrate | TSMC roadmap, April 2026, as reported | | **2028** | 14x, about 12,000 mm² | 20 stacked compute chiplets and 20 HBM5 | TSMC roadmap, as reported | | **2029** | More than 14x | Up to 24 HBM5E | TSMC roadmap, as reported | *The 2024 row is Nvidia’s figure; 2027–2029 are TSMC plans reported from its April 2026 symposium, not products. The 14x area is our arithmetic (14 × 858 mm²). Sources under References.* Our read on the clock: the size of the largest package is more than doubling every two years on TSMC’s plan, from about two reticles in 2024 to five now and 14 in 2028\. Packaging capacity has to keep pace with that, and the capacity side is tracked in [TSMC CoWoS capacity](https://www.sotkn.com/markets/taiwan/tsmc-cowos-capacity/). The wafer side of the same quarter is in our [Wire on TSMC’s third-quarter results](https://www.sotkn.com/wire/tsmc-q3-2026-2nm-8-percent-demand-above-supply-wire/). ## What chiplets do not tell you A chiplet count is not a performance number. Nvidia uses two big dies and AMD uses many smaller ones, and both are aimed at the same AI work. More pieces mean more flexibility in manufacturing, not a faster chip by themselves. Nor does it say who wins the socket. Custom accelerators built for one cloud company use the same building blocks; [who makes custom AI chips](https://www.sotkn.com/explained/who-makes-custom-ai-chips/) covers those designers. And once the chips leave the package, the next limit is the rack and the power behind it; see [rack-scale AI](https://www.sotkn.com/explained/rack-scale-ai-explained/). ## What would prove this wrong? - **Packaging stops being short.** If TSMC’s next calls describe packaging capacity as balanced, the stuck step has moved elsewhere, such as memory, substrates or power. - **The big designs go back to fewer pieces.** If the next generation of accelerators uses fewer, larger dies, the join matters less and the wafer matters more. - **Join yields jump.** If large packages lose far fewer good dies, the cost of joining falls and the savings from splitting grow. ## What to check next TSMC’s fourth-quarter 2026 earnings call, expected in January 2027, for any change in how far demand runs ahead of packaging supply and whether nine-times-reticle packages reach production. How the MI455X ramps in AMD’s next quarterly results. Nvidia’s next product details for how many dies its following GPUs use. And any interposer supply arriving early; see our [Wire on GlobalFoundries’ $2 billion interposer deal](https://www.sotkn.com/wire/globalfoundries-tsmc-2b-silicon-interposer-wire/). ## Common misconceptions - **People assume a chiplet is a small, cheap chip.** Actually a chiplet can be huge: each of Blackwell’s two dies sits at the reticle limit of about 858 square millimetres. - **People assume chiplets are always cheaper.** Actually the joining adds cost; in a 2022 cost model packaging took about 30% of the total in a 16-core example, and up to half in large side-by-side packages. - **People assume all chiplets use the newest process.** Actually AMD kept its MI355X I/O dies on the older N6 process because those circuits do not shrink well. - **People assume an open standard links today’s AI chiplets.** Actually Nvidia and AMD join their own dies with their own links; UCIe matters most for mixing dies from different suppliers. ## FAQ **What is a chiplet?** A chiplet is a small chip die designed to be joined with other dies inside one package, so that together they work as a single processor. Each die can be made separately, tested, and then assembled. **What is the difference between a chiplet and a monolithic chip?** A monolithic chip puts the whole design on one die. A chiplet design splits it across several dies joined inside the package. Monolithic avoids the cost of joining; chiplets get past the size limit of one die and waste less silicon to defects. **Why do AI chips use chiplets?** Because the biggest single die a lithography tool can print is about 26 by 33 millimetres, and AI chips need more transistors than that. Nvidia’s Hopper die was 814 square millimetres; Blackwell joins two dies of about that size to pass 1,600. **Does Nvidia use chiplets?** Yes, in its own way. Blackwell joins two reticle-limited compute dies with a 10 TB/s link so software sees one GPU, and Rubin, described in July 2026, keeps the two-die design. AMD splits further: its MI455X has 12 logic dies and 12 memory stacks on one package. **What is UCIe?** UCIe, Universal Chiplet Interconnect Express, is an open standard for links between chiplets in one package. Its consortium formed in March 2022 and released version 3.0 on 5 August 2025, with speeds up to 64 GT/s. **Are chiplets cheaper than one big chip?** Each die is cheaper because small dies lose less to defects, but joining them adds cost. A 2022 academic cost model found AMD-style designs could save up to half of the die cost, while packaging took about 30% of total cost in one 16-core example. **Is this a list of stocks to buy or sell?** No. Second Order Explained pages explain how a mechanism works and where the money moves. They do not give buy or sell calls. Not investment advice. Do your own research. Related: [interposer](https://www.sotkn.com/explained/interposer-explained/); [CoWoS](https://www.sotkn.com/explained/cowos-explained/); [CoWoS vs EMIB](https://www.sotkn.com/explained/cowos-vs-emib/); [hybrid bonding](https://www.sotkn.com/explained/hybrid-bonding-explained/); [HBM](https://www.sotkn.com/explained/hbm-explained/); [IC substrates and ABF](https://www.sotkn.com/explained/ic-substrates-abf-explained/); [foundry and advanced packaging](https://www.sotkn.com/explained/foundry-advanced-packaging-explained/). ## Stack doors Layer: [Semiconductors](https://www.sotkn.com/stack/semiconductors/) ([CoWoS](https://www.sotkn.com/stack/semiconductors/cowos/), [HBM](https://www.sotkn.com/stack/semiconductors/hbm/)). Also: [Neoclouds](https://www.sotkn.com/stack/neoclouds/), [Hyperscalers](https://www.sotkn.com/stack/hyperscalers/), [AI Data Centers](https://www.sotkn.com/stack/ai-data-centers/). Markets: [Taiwan](https://www.sotkn.com/markets/taiwan/), [US](https://www.sotkn.com/markets/us/), [Korea](https://www.sotkn.com/markets/korea/). [Get the Wire](https://www.sotkn.com/#/portal/signup) — short daily notes when packaging capacity, chip designs and AI chip supply move. Not investment advice. Do your own research. **How we check this** Nvidia’s die sizes and Blackwell figures come from its Hot Chips 2024 presentation, and Rubin’s from its 21 July 2026 technical blog. AMD’s chiplet layouts come from its CDNA 4 and CDNA 5 white papers and its MI455X product page. The UCIe figures come from the consortium’s 5 August 2025 release. The cost findings come from a peer-reviewed 2022 paper presented at the Design Automation Conference, and are labelled as a model, not as any company’s costs. TSMC’s production status comes from its 15 October 2026 earnings call; its 2027–2029 package plans come from a report on its April 2026 technology symposium and are labelled as reported. Each was re-checked on 20 Oct 2026\. Company figures are the companies’ own. Where we work something out ourselves it is labelled “our arithmetic”, and where we interpret it is labelled “our read”. This page explains a mechanism. It does not give buy or sell calls. Not investment advice. Do your own research. **Last reviewed:** 20 Oct 2026 · **Next review:** after TSMC's fourth-quarter 2026 earnings call in January 2027 Spot an error? [Tell us](mailto:sean@thekopinotes.com) and we will correct it and note the change here. [Our editorial standards →](https://www.sotkn.com/editorial-standards/) ## References 1. [NVIDIA — Blackwell platform, Hot Chips 2024 presentation (Aug 2024)](https://www.hc2024.hotchips.org/assets/program/conference/day1/64%5FHC2024.NVIDIA.TirumalaWong.pdf?ref=sotkn.com) — die sizes of Volta, Ampere and Hopper; Blackwell as two reticle-limited dies, over 1,600 mm², 208 billion transistors, 10 TB/s NV-HBI link, eight HBM3e sites 2. [NVIDIA Technical Blog — Inside NVIDIA Rubin GPU architecture (21 Jul 2026)](https://developer.nvidia.com/blog/inside-nvidia-rubin-gpu-architecture-powering-the-era-of-agentic-ai/?ref=sotkn.com) — Rubin built from two reticle-limited compute dies joined by NV-HBI; 336 billion transistors; 288 GB of HBM4 3. [AMD — CDNA 4 architecture white paper, Instinct MI350 Series (Jun 2025)](https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/white-papers/amd-cdna-4-architecture-whitepaper.pdf?ref=sotkn.com) — eight compute dies on N3P stacked on two I/O dies on N6; 185 billion transistors; 32 of 36 compute units active for yield 4. [AMD — CDNA 5 architecture white paper, Instinct MI455X (2026)](https://www.amd.com/content/dam/amd/en/documents/products/technologies/cdna/amd-cdna5-whitepaper.pdf?ref=sotkn.com) — compute dies on TSMC N2, fabric-and-cache and I/O dies on N3P; 8 + 2 + 2 dies and 12 HBM4 stacks; 320 billion transistors 5. [AMD — Instinct MI455X product page (launched 23 Jul 2026)](https://www.amd.com/en/products/accelerators/instinct/mi400/mi455x.html?ref=sotkn.com) — launch date, 432 GB of HBM4 in 12 stacks, 23.3 TB/s 6. [UCIe Consortium — specifications page, UCIe 3.0 (released 5 Aug 2025)](https://www.uciexpress.org/specifications?ref=sotkn.com) — open die-to-die standard; 48 and 64 GT/s, double UCIe 2.0's 32 GT/s 7. [Feng and Ma — Chiplet Actuary: a quantitative cost model for multi-chiplet systems (Design Automation Conference 2022)](https://arxiv.org/abs/2203.12268?ref=sotkn.com) — defect cost, die-cost savings, packaging overhead and wasted known good dies 8. [TSMC — Q3 2026 quarterly results and earnings conference transcript (15 Oct 2026)](https://investor.tsmc.com/english/quarterly-results/2026/q3?ref=sotkn.com) — 5x-reticle packages in production, 9x and 14x in development; demand far above supply 9. [Tom's Hardware — TSMC details next-gen CoWoS roadmap at its 2026 North American Technology Symposium (27 Apr 2026)](https://www.tomshardware.com/tech-industry/semiconductors/tsmcs-details-next-gen-cowos-roadmap-over-14-reticle-packages-and-48x-leap-in-compute-power-expected-by-2029-massive-size-enables-24-hbm5e-stacks-and-additional-memory-bandwidth-jump?ref=sotkn.com) — reticle of 26 × 33 mm; 9.5-reticle in 2027, 14-reticle with 20 compute chiplets and 20 HBM5 stacks in 2028 10. [Wikimedia Commons — AMD Epyc 7702 delidded, near-infrared photo by Fritzchens Fritz, CC0 (taken 21 Oct 2019)](https://commons.wikimedia.org/wiki/File:AMD%5FEpyc%5F7702%5Fdelidded.jpg?ref=sotkn.com) — featured image base photo S **[Sean](https://www.sotkn.com/author/sean/)** Writes Second Order by TKN — a plain-English map of AI infrastructure and semiconductors for non-specialist investors. Focus: who gets paid, where money sticks, and which step is stuck. Covers AI infrastructure, semiconductors, and second-order stack reads. [Author page →](https://www.sotkn.com/author/sean/) · [Editorial standards →](https://www.sotkn.com/editorial-standards/)