> ## Content Index > Fetch the complete content index at: https://www.sotkn.com/llms.txt > Use this file to discover other available public pages before exploring further. # What Is an HBM Base Die? Why the Logic Under the Stack Gets Paid - URL: https://www.sotkn.com/explained/hbm-base-die-explained/ - Published: 2026-11-04T01:16:06.000Z - Updated: 2026-11-04T01:16:06.000Z - Description: An HBM base die is the logic chip under a memory stack. It drives the wires to the processor. At HBM4 that die is increasingly a foundry wafer, and that wafer is a second invoice. - Author: Sean - Tags: #desk-explained, Mechanism EXPLAINED · Mechanism · Last reviewed: 4 Nov 2026 · Next review: after Samsung's and SK hynix's fourth-quarter results in late January 2027 An HBM base die is the logic chip at the bottom of a high-bandwidth memory stack. The DRAM dies above it hold the bits. The base die moves those bits between the stack and the processor beside it. In short. The memory maker sells the finished stack. The chip underneath is increasingly a foundry logic wafer, and that wafer is a second invoice. Samsung has said base-die sales already moved its foundry earnings. SK hynix has said its HBM4 base die uses a TSMC logic process. Our read: the stuck step is that logic wafer and, on a custom die, the design cycle shared with the customer's accelerator. Our guide to [HBM](https://www.sotkn.com/explained/hbm-explained/) covers the stack. This page covers the die under it. ## What is an HBM base die? It is the bottom chip in the cube. On 8 July 2026 SK hynix defined it as the die at the bottom of an HBM stack that handles data in, data out, and control, between the DRAM dies and an external logic chip such as a GPU. The same note says "logic die" when the point is that control job. Micron's HBM4 page splits the build into three wafers. One is DRAM dies with through-silicon vias, the vertical pipes through the stack. One is the thicker top die, which closes the cube. One is the logic die, which faces the system. Only tested dies are stacked, and the DRAM goes on the logic die. The cube is then placed beside the accelerator. That placement is packaging, covered in [CoWoS](https://www.sotkn.com/explained/cowos-explained/). The base die is already in the cube before it. Micron's volume part is a 12-high, 36 GB stack. It has also sampled a 16-high, 48 GB stack. One logic die under twelve or sixteen memory dies. Micron calls the taller cube 33 percent more capacity per placement. Our check: 48 divided by 36 is 1.33. ## What does the base die do? It drives the wires between the stack and the processor. The DRAM dies store. The base die presents the interface. JEDEC published HBM4, JESD270-4, on 16 April 2025\. The standard page says HBM4 is tightly coupled to the host compute die, in independent channels, each a 64-bit bus at double data rate. The press note sets the pace: up to 8 gigabits per second across 2,048 bits, stated as up to 2 terabytes per second, and 32 channels against 16 in HBM3. Our arithmetic: 2,048 times 8, divided by 8, is 2,048 gigabytes per second, which is the "up to 2 TB/s." Thirty-two channels times 64 bits is also 2,048\. JEDEC allows the data-line voltage at 0.7, 0.75, 0.8 or 0.9 volts. A bus that wide, with room to drop the voltage, is a logic circuit. The cubes it has to serve run from 4-high to 16-high, up to 64 GB. The base die stores none of those gigabytes. It opens the channels. ## Why does HBM4 change the base die? Because the interface doubled, and the work started to look like logic. Shipping parts already run past JEDEC's ceiling. On 10 June 2025 Micron said its HBM4 samples used a 2,048-bit interface at more than 2.0 TB/s, with a ramp planned for calendar 2026\. On 16 March 2026 it said volume shipment of the 36 GB 12-high had begun in the first quarter of calendar 2026, for Nvidia's Vera Rubin platform, at pin speeds over 11 gigabits per second and bandwidth greater than 2.8 TB/s. Micron called that 2.3 times the bandwidth of its own HBM3E, and more than 20 percent better power efficiency, on its own comparison. Our arithmetic on the pin speed Micron named: 2,048 times 11 gigabits per second, divided by 8, is 2,816 gigabytes per second, about 2.8 TB/s. "Greater than 11" is why the bandwidth can be "greater than 2.8." The bottom die has to drive that. The three makers have not described the same process. | Maker | What it has said about the base die | What it has not said | | --------------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | --------------------------------------- | | Samsung Foundry | 30 July 2026: foundry earnings up on base-die demand, before incentive provisions; more 4nm base-die sales planned. 29 October 2026: foundry revenue and earnings up on that growth. The PDF says "HBM B-Die." | Any separate revenue, or a wafer share. | | SK hynix | 8 July 2026: a TSMC advanced logic process on the base die from HBM4\. Same note: custom HBM fits that die to the customer's chip. | A node number for the TSMC process. | | Micron | HBM4 notes name the 1-beta DRAM process, not a foundry. 18 March 2026: HBM4E, with customization, aimed at calendar 2027 on 1-gamma DRAM. | A foundry node for the HBM4 base die. | Samsung Foundry's custom-HBM note, which carries no date, goes one step on. It puts the memory controller and a die-to-die link on a foundry base die, under the stack. That is a description, not a shipment. ## Who gets paid — and where is the stuck step? Our read: the memory maker still invoices the GPU buyer for the stack, and a foundry now invoices the memory maker for the die underneath. - The memory maker is paid for a qualified stack. SK hynix, Samsung and Micron are that invoice. See [who makes HBM](https://www.sotkn.com/explained/who-makes-hbm/). - The foundry is paid for the logic wafer. Samsung has said so twice in 2026\. Second-quarter foundry earnings improved on HBM base-die demand, with more 4nm base-die sales planned. On 29 October it said third-quarter foundry revenue and earnings improved on that sales growth, beside further 2nm orders from high-performance computing customers, including major hyperscalers. Device Solutions, which houses the foundry, reported KRW 147.1 trillion of revenue and KRW 106.5 trillion of operating profit. Foundry is not broken out. Named, not sized. - TSMC is paid where SK hynix has moved the die. The 8 July note says a TSMC advanced logic process on the base die from HBM4\. On 11 June the SK hynix newsroom reported chairman Chey Tae-won at Computex: "We're collaborating on HBM4, and we have an excellent partnership with TSMC." The stuck step is that wafer, then the drawing of a custom die. A DRAM line and a logic line are different queues. On 4nm, or on a TSMC logic process, the base die waits behind phone chips and accelerators. A small die yields more kindly than a big accelerator, which is the point of our [yield](https://www.sotkn.com/explained/semiconductor-yield-explained/) page, and kind yield still adds no slot. Samsung put the base die and [2nm](https://www.sotkn.com/explained/2nm-chip-explained/) orders in one foundry paragraph. Custom pulls the wait forward. SK hynix fits the custom die to one customer's chip, power and heat, and names HBM4E and custom HBM next. Samsung Foundry puts the memory controller on that die. Micron, on 18 March 2026, tied HBM4E customization to a deeper research engagement and a calendar 2027 ramp. A catalogue die is ordered to a standard. A custom die is drawn with the accelerator first. Cash sticks at the foundry, and on a custom die it sticks in that design cycle. ## Why does it bind? A late base die leaves good DRAM with no way to present 2,048 wires. Late DRAM leaves a logic die with an empty stack. Either miss holds the cube, and the cube holds the accelerator package. [CoWoS](https://www.sotkn.com/explained/cowos-explained/) attaches a finished stack. It does not finish one. Power lands on the same die: JEDEC's lower voltages, Micron's claim of more than 20 percent better efficiency than its own HBM3E, and a foundry process that spends less power than a memory process. ## What would change the view? - A number. If Samsung, TSMC or SK hynix publishes base-die revenue or a share of foundry wafers, the "named, not sized" line on this page becomes a figure. - The paths converge. If Micron's public account of HBM4E names a foundry logic process, as SK hynix has for HBM4, the foundry invoice becomes the common path. - The catalogue part wins. If HBM4E ships as a standard die and custom logic stays a slide, the stuck step stays on the DRAM process and the stack. - Samsung's next results stop naming base-die sales as a foundry driver. Then the demand in the July and October 2026 notes has cooled. ## Common misconceptions - People assume the base die is another DRAM die. SK hynix defines it as the input, output and control die, and says that from HBM4 its process is part of the product. - People assume the memory maker keeps every dollar in the cube. Samsung has said base-die sales moved foundry revenue and earnings. That is a foundry invoice inside a memory product. - People assume the three suppliers build it the same way. Samsung has named a 4nm foundry die. SK hynix has named a TSMC logic process from HBM4\. Micron's HBM4 notes name its DRAM process and do not name a foundry node. - People assume a wider bus is only a packaging problem. Packaging joins a finished cube to the GPU. The 2,048 wires are driven by the bottom die before that join exists. - People assume a custom base die is only a slogan. Samsung Foundry describes a controller moved onto the die. SK hynix describes a die fit to one customer's chip. Micron describes a deeper research engagement on HBM4E. Those are design statements, and none of the three has published a custom volume. ## FAQ What is an HBM base die? An HBM base die is the logic chip at the bottom of a high-bandwidth memory stack. It handles data in, data out and control between the DRAM dies and the processor. SK hynix published that definition on 8 July 2026. What does the base die do? It drives the wires the processor uses to reach the stack. JEDEC's HBM4 standard of 16 April 2025 sets that interface at up to 8 gigabits per second across 2,048 bits, up to 2 terabytes per second, on 32 channels. Why does the base die change at HBM4? The interface is wider, so the circuit behaves like logic. SK hynix says that from HBM4 it uses a TSMC logic process. Samsung says it sells base-die products on its 4nm process. Who gets paid for the base die? The memory maker is paid for the finished stack. The foundry is paid for the logic wafer. Samsung said on 29 October 2026 that foundry revenue and earnings improved on HBM base-die sales growth, and published no separate figure. Where is the stuck step? On the logic wafer and, for a custom base die, in the design cycle with the customer's accelerator. The stack cannot present 2,048 wires without the die, and a custom die is drawn before the wafers run. Do Samsung, SK hynix and Micron build the base die the same way? They have described three paths. Samsung names a 4nm foundry die. SK hynix names a TSMC logic process from HBM4\. Micron's HBM4 notes name its DRAM process and do not name a foundry node. Is this a list of stocks to buy or sell? No. This page explains the HBM base die and where cash sticks. It does not rank companies or give buy or sell calls. Not investment advice. Do your own research. ## Related terms - [HBM](https://www.sotkn.com/explained/hbm-explained/) — the stack this die sits under. - [CoWoS](https://www.sotkn.com/explained/cowos-explained/) — the join that puts a finished cube beside the accelerator. - [Semiconductor yield](https://www.sotkn.com/explained/semiconductor-yield-explained/) — why a small logic die loses less of a wafer than a large one, and why that still adds no fab. - [2nm chips](https://www.sotkn.com/explained/2nm-chip-explained/) — the advanced-node queue Samsung's foundry named beside base-die sales. - [Who makes HBM](https://www.sotkn.com/explained/who-makes-hbm/) — the three memory makers on the stack invoice. - [Hybrid bonding](https://www.sotkn.com/explained/hybrid-bonding-explained/) — a way to join dies in a tall stack, separate from the base die's logic process. - [Chiplets](https://www.sotkn.com/explained/chiplet-explained/) — putting one job on its own die. A custom base die does that inside the cube. ## Markets and stack doors Layer: [Semiconductors](https://www.sotkn.com/stack/semiconductors/). The base die is a logic wafer sold into a memory product, so it sits on this layer. Markets: [Taiwan](https://www.sotkn.com/markets/taiwan/), where TSMC runs the logic process SK hynix has named for its HBM4 base die. [Korea](https://www.sotkn.com/markets/korea/), where Samsung Foundry has put 4nm base-die sales in its results and where SK hynix designs the stack. [United States](https://www.sotkn.com/markets/us/), where Micron's HBM4 notes still describe the logic die inside its own flow. Not investment advice. Do your own research. ## How we check this Definitions and the TSMC sentence are from SK hynix on 8 July 2026\. Chey's line is from its Computex account on 11 June 2026\. Samsung's foundry lines are from 30 July and 29 October 2026, and "HBM B-Die" is from the October earnings PDF. The controller description is Samsung Foundry's undated tech blog, retrieved 4 November 2026, used as a description and not a shipment. JEDEC's figures are the 16 April 2025 release and the JESD270-4A page. Micron's figures are its 10 June 2025 and 16 March 2026 releases, its HBM4 page, and the 18 March 2026 prepared remarks. Pin-speed, 48-over-36 and channel products are our arithmetic. Who gets paid, and the stuck step, are our read. Not investment advice. Do your own research. Last reviewed: 4 Nov 2026 · Next review: after Samsung's and SK hynix's fourth-quarter results in late January 2027 ## Sources 1. [SK hynix, 8 Jul 2026](https://news.skhynix.com/en/hbm-to-essd/?ref=sotkn.com) — base-die definition, TSMC logic process from HBM4, custom HBM. 2. [SK hynix newsroom, 11 Jun 2026](https://news.skhynix.com/en/computex-2026-review/?ref=sotkn.com) — Chey on the TSMC partnership for HBM4. 3. [Samsung results, 30 Jul 2026](https://news.samsung.com/global/samsung-electronics-announces-second-quarter-2026-results?ref=sotkn.com) — foundry earnings on base-die demand; 4nm base-die plan. 4. [Samsung results, 29 Oct 2026](https://news.samsung.com/global/samsung-electronics-announces-third-quarter-2026-results?ref=sotkn.com) — foundry improvement on base-die sales; Device Solutions KRW 147.1 trillion revenue, KRW 106.5 trillion operating profit. 5. [Samsung earnings PDF, 29 Oct 2026](https://images.samsung.com/is/content/samsung/assets/global/ir/docs/2026%5F3Q%5Fconference%5Feng.pdf?ref=sotkn.com) — "HBM B-Die." 6. [Samsung Foundry tech blog, retrieved 4 Nov 2026](https://semiconductor.samsung.com/news-events/tech-blog/advancing-high-performance-compute-with-customized-foundry-logic-memory-integration/?ref=sotkn.com) — controller on a foundry base die. Undated. Not a shipment. 7. [JEDEC HBM4 release, 16 Apr 2025](https://www.jedec.org/news/pressreleases/jedec%C2%AE-and-industry-leaders-collaborate-release-jesd270-4-hbm4-standard-advancing?ref=sotkn.com) — 2,048-bit interface, up to 8 Gb/s, up to 2 TB/s, 32 channels. 8. [JEDEC JESD270-4A, Dec 2025](https://www.jedec.org/standards-documents/docs/jesd270-4a?ref=sotkn.com) — 64-bit channel bus. 9. [Micron HBM4 page, retrieved 4 Nov 2026](https://www.micron.com/products/memory/hbm/hbm4?ref=sotkn.com) — three wafers; above 11 Gb/s and 2.8 TB/s. 10. [Micron, 10 Jun 2025](https://investors.micron.com/news/press-release/2025/Micron-Ships-HBM4-to-Key-Customers-to-Power-Next-Gen-AI-Platforms-06-10-2025/default.aspx?ref=sotkn.com) — 36 GB samples, above 2.0 TB/s, 1-beta DRAM. 11. [Micron, 16 Mar 2026](https://investors.micron.com/news/press-release/2026/Micron-in-High-Volume-Production-of-HBM4-Designed-for-NVIDIA-Vera-Rubin-PCIe-Gen6-SSD-and-SOCAMM2-03-16-2026/default.aspx?ref=sotkn.com) — volume for Vera Rubin; 2.3 times its HBM3E; 48 GB samples. 12. [Micron prepared remarks, 18 Mar 2026](https://investors.micron.com/static-files/9c0becf5-df56-4eec-bd67-453dda68b273?ref=sotkn.com) — HBM4E in calendar 2027, with customization.