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# What Is Hybrid Bonding? Copper-to-Copper Joins for AI Stacks
- URL: https://www.sotkn.com/explained/hybrid-bonding-explained/
- Published: 2026-10-05T01:11:11.000Z
- Updated: 2026-10-05T01:11:11.000Z
- Description: Hybrid bonding stacks dies copper-to-copper. Logic is in volume; HBM4 still ships on microbumps. Who gets paid, and which clock is stuck.
- Author: Sean
- Tags: #desk-explained, Mechanism

EXPLAINED · Mechanism · Last reviewed: 5 Oct 2026 · Next review: after Besi Q3 2026 results (22 Oct 2026) print hybrid-bonding orders against memory evaluations

Hybrid bonding is the join that stacks two dies by mating polished copper pads in a dielectric field — no solder microbump in between. The foundry or assembler activates the surfaces, aligns the pads, and lets copper expand into a permanent electrical and mechanical bond.

**In short.** Hybrid bonding is how the [semiconductors](https://www.sotkn.com/stack/semiconductors/) layer stacks logic on logic today. TSMC SoIC 3-nanometre chip stacking entered volume in 2025\. Besi counted **21** hybrid-bonding customers at end-Q2 2026, up from **15** at year-end 2025\. The stuck step is which interface uses it. [HBM](https://www.sotkn.com/explained/hbm-explained/) beside an AI die in [CoWoS](https://www.sotkn.com/explained/cowos-explained/) is a neighbour clock: SK hynix began **HBM4 mass shipments in Q2 2026** without presenting that generation as a hybrid-bonding product.

Who gets paid when more AI packages need a copper join — the logic bonder already shipping, or the HBM stack that has not switched.

## What is hybrid bonding?

A conventional 2.5D package joins dies with solder microbumps. The bump has height, resistance, and a pitch floor. Hybrid bonding removes the bump. Copper pads in an oxide (or similar dielectric) field are planarised, activated, aligned, and bonded. Electrical contact and mechanical hold are the same step.

Two placements matter, because they are not the same tool clock.

| Placement                 | What is joined                      | Pitch class                                  | 2026 volume print                            |
| ------------------------- | ----------------------------------- | -------------------------------------------- | -------------------------------------------- |
| Wafer-to-wafer            | Two full wafers, then dice          | Tightest (lab pitches well below production) | High-yielding, same-size dies                |
| Die-to-wafer              | Known-good dies placed onto a wafer | Production logic stacks                      | TSMC SoIC volume; Besi/Applied Kinex lines   |
| Die-to-die (in a package) | Chiplet on chiplet after dicing     | Sub-10 µm on Intel Foveros Direct            | Dedicated 3D stack, not the CoWoS HBM attach |

Intel's Foveros Direct 3D brief puts the copper-to-copper pitch in the **sub-10 µm** class — “up to 10× finer interconnect density compared to conventional microbump technologies.” The same brief still lists Foveros 2.5D at **36 µm** microbumps. **Our check:** 36 ÷ 10 = **3.6×** at the 10 µm floor Intel named; the “up to 10×” line is against a coarser conventional bump, not that 36 µm Foveros row.

TSMC's SoIC page is the foundry volume print: bond pitch “starts from the sub-10µm rule,” and “3nm chip stacking technology successfully entered volume production in 2025.” The 22 Apr 2026 North America Technology Symposium set the next density step: **A14-to-A14 SoIC** for production in **2029**, with **1.8×** higher die-to-die I/O density than **N2-on-N2 SoIC**. That is a logic-on-logic roadmap, not a statement that HBM cubes will ride the same bond.

Applied Materials' Kinex system is the die-to-wafer tool: an integrated clean / plasma-activation / bond / metrology line co-developed with Besi. Besi's 23 Jul 2026 release is the seller invoice behind that line.

Hybrid bonding sits *inside* a stack. [CoWoS](https://www.sotkn.com/explained/cowos-explained/) is the package that still parks HBM beside a compute die on an interposer or RDL. [EUV](https://www.sotkn.com/explained/euv-lithography-explained/) prints the die before anyone bonds it. Those are neighbour clocks.

## Why does it bind?

It binds because the copper join is qualified on logic first, while the HBM cube that every AI accelerator still needs has not been shown as a volume hybrid-bonding product in 2026 company prints.

Besi is the dated assembly-tool print. Q2 2026 revenue was **€249.9 million**, up **68.7%** from €148.1 million. Orders were **€292.9 million**, up **128.8%** from €128.0 million. Last-twelve-month orders hit a record **€987.6 million**. H1 orders were **€562.6 million**, up **€302.7 million** (**116.5%**) versus H1 2025\. Richard Blickman said hybrid-bonding customers rose from **15** at year-end 2025 to **21** at end-Q2 2026 — logic, memory, co-packaged optics and consumer — and that Q2 hybrid-bonding orders included **two repeat customers and one new hyperscaler**. AI system orders were about **60%** of H1 2026 versus about **50%** in H1 2025 (23 Jul 2026 release).

**Our arithmetic on the guide:** Q3 2026 revenue is expected up **10–15%** versus €249.9 million. 249.9 × 1.10 = **€274.9 million**; × 1.15 = **€287.4 million**. That is a logic-and-photonics bonder clock. Blickman did not disclose hybrid-bonding unit shipments. On the 23 Jul 2026 call he said HBM hybrid bonding was still in evaluation at one of the three memory companies, with another starting, and that “some are voicing that it may delay. Others are voicing that it is imminent.” An evaluation is not a cube in a CoWoS slot.

The memory print sits in Korea. SK hynix's 29 Jul 2026 newsroom said it began **mass shipments of HBM4 in the second quarter** and will ramp in the second half. Q2 revenue was **79.3187 trillion won**, operating profit **60.5426 trillion won**. **Our check:** 60.5426 ÷ 79.3187 = **76.3%**, the 76% operating margin in that release. That invoice is HBM4 volume, not a hybrid-bonding invoice.

The foundry print sits in Taiwan. TSMC's 22 Apr 2026 symposium is still scaling **CoWoS** to park more HBM beside compute: a **14-reticle** version “capable of integrating approximately 10 large compute dies and 20 HBM stacks” slated for **2028**. SoIC is listed in the same release as a separate 3D stacking offer (A14-to-A14 in 2029). Two sentences, two interfaces. C.C. Wei on the 16 Jul 2026 call still described advanced-packaging capacity as tight enough to limit customer growth — the CoWoS-class slot, not the SoIC bond pitch.

Intel's Foveros Direct brief is the US method: copper-to-copper, no microbump, sub-10 µm. Intel launched **Xeon 6+** on 1 Jun 2026 as its first data-centre CPU on Intel 18A. An earlier foundry write-up named Clearwater Forest as 18A compute chiplets stacked with **Foveros Direct 3D** onto a base die, then tied with EMIB. That is a logic 3D clock in a server CPU. It does not move the HBM cube beside an accelerator.

## Who gets paid — and where is the stuck step?

On the semiconductors layer, who gets paid tracks which join has cleared.

| Step         | Who                                                      | Why it matters                                                                  |
| ------------ | -------------------------------------------------------- | ------------------------------------------------------------------------------- |
| Bond tool    | Besi (placement) + Applied Materials (prep / Kinex line) | 21 hybrid-bonding customers; Q2 orders €292.9m; AI \~60% of H1 system orders    |
| Logic stack  | TSMC SoIC; Intel Foveros Direct                          | Volume on logic-on-logic; 2025 SoIC 3 nm; 2029 A14-on-A14 density step          |
| Stuck step   | HBM interface still on bumps                             | HBM4 is shipping (SK hynix Q2 2026); Besi still called memory use an evaluation |
| Package slot | TSMC CoWoS (and like-kind)                               | 14-reticle CoWoS in 2028 still counts **20 HBM stacks** beside compute          |
| Buyer        | Hyperscalers and accelerator designers                   | Pay for a module. They do not buy a bonder                                      |

Cash sticks at Besi when a hybrid-bonding system is ordered and recognised — Q2 net income **€89.0 million**, net margin **35.6%**. Cash sticks at the foundry when SoIC-stacked logic yields and when CoWoS slots fill. Cash sticks at SK hynix when HBM4 cubes ship under long agreements, whether or not those cubes are copper-bonded. Cash sticks at Applied on the clean/activate/metrology steps around the bonder.

The Taiwan door is SoIC volume plus the CoWoS slot that still attaches HBM. Korea is HBM4 allocation on today's stack method. The US door is Foveros Direct on an 18A server CPU, and the Kinex/Besi tool invoice.

A useful test, not a ticker call: if Besi's 22 Oct 2026 Q3 print shows hybrid-bonding orders still led by logic, photonics and a hyperscaler repeat, while SK hynix's next results still describe HBM4 as a ramp of the current stack, the copper join is converting on logic and waiting on memory. If a memory house names hybrid bonding as the HBM4E or HBM5 production method, the neighbour clock has moved.

## Common misconceptions

- **People assume hybrid bonding is the same gate as CoWoS.** Actually CoWoS places an HBM cube beside a compute die. Hybrid bonding stacks copper pads. TSMC listed both a 14-reticle CoWoS for 2028 and a separate SoIC step for 2029\. See [CoWoS explained](https://www.sotkn.com/explained/cowos-explained/).
- **People assume HBM4 volume means hybrid bonding is in the cube.** Actually SK hynix printed HBM4 mass shipments in Q2 2026\. Besi's 23 Jul 2026 call still called HBM hybrid bonding an evaluation.
- **People assume a Besi order spike is an HBM-stack spike.** Actually Q2 hybrid-bonding orders included two repeat customers and one new hyperscaler. Unit shipments were not disclosed.
- **People assume SoIC replaced CoWoS.** Actually TSMC's SoIC page says SoIC chips can be subsequently assembled in CoWoS or SoW.
- **People assume Intel's 18A CPU launch is the accelerator HBM clock.** Actually Xeon 6+ (1 Jun 2026) is a data-centre CPU. The HBM cube beside an AI GPU is still the Korea/Taiwan neighbour.

Not investment advice. Do your own research.

## FAQ

**What is hybrid bonding?**  
Hybrid bonding is the join that stacks two dies by mating polished copper pads in a dielectric field, with no solder microbump in between. TSMC SoIC 3-nanometre chip stacking entered volume production in 2025\. Intel's Foveros Direct brief puts the copper-to-copper pitch in the sub-10 µm class.

**How is hybrid bonding different from CoWoS?**  
Hybrid bonding is a die-to-die or die-to-wafer copper join. CoWoS is TSMC's package family that places compute and HBM on an interposer or RDL. TSMC's April 2026 symposium still plans a 14-reticle CoWoS with about 10 compute dies and 20 HBM stacks for 2028, listed separately from SoIC.

**Why doesn't HBM4 use hybrid bonding yet?**  
SK hynix began HBM4 mass shipments in Q2 2026 and is ramping in the second half. That is a volume print for the cube, not a hybrid-bonding print. Besi said on 23 Jul 2026 that hybrid bonding for HBM was still in evaluation at memory companies, with some voices saying delay and others saying imminent.

**Who gets paid when hybrid bonding ramps?**  
Besi and Applied Materials get paid when bonders and prep lines are ordered and recognised. Foundries get paid when SoIC-class logic stacks yield. Memory houses get paid when HBM cubes ship, even if those cubes still use microbumps. The stuck step is the HBM interface, not the existence of copper bonding on logic.

**Is hybrid bonding the same as SoIC?**  
SoIC is TSMC's wafer-level 3D stacking service that uses a hybrid-bonding scheme at sub-10 µm pitch. Hybrid bonding is the join. SoIC is one foundry product that uses it. Intel's Foveros Direct is another. CoWoS can still wrap a SoIC chip and attach HBM beside it.

**Does a Besi order spike mean HBM stacks just got faster?**  
No. Besi's Q2 2026 orders rose 128.8% to €292.9 million, and hybrid-bonding customers rose from 15 to 21\. Blickman tied Q2 hybrid-bonding orders to two repeat customers and one new hyperscaler, and still described HBM use as an evaluation. Logic and photonics can fill a bonder queue without a memory-cube switch.

**What would change the view?**  
A memory house naming hybrid bonding as the production method for HBM4E or HBM5, or TSMC moving HBM attach onto SoIC-class bonds. Until then, treat Besi's 22 Oct 2026 Q3 print as a logic-bonder check, not an HBM-cube check.

## Related terms

- [CoWoS](https://www.sotkn.com/explained/cowos-explained/) — the package that still parks HBM beside compute; a neighbour clock, not the copper join.
- [HBM](https://www.sotkn.com/explained/hbm-explained/) — the stacked DRAM the accelerator still needs beside the die.
- [EUV lithography](https://www.sotkn.com/explained/euv-lithography-explained/) — the scanner step that prints the die before anyone bonds it.
- [Foundry and advanced packaging](https://www.sotkn.com/explained/foundry-advanced-packaging-explained/) — the wider finish line after lithography.
- [Who makes HBM](https://www.sotkn.com/explained/who-makes-hbm/) — the memory names that get paid when cubes ship.

## Markets and stack doors

Layer: [semiconductors](https://www.sotkn.com/stack/semiconductors/). Sibling layers: [hyperscalers](https://www.sotkn.com/stack/hyperscalers/) (who buy the modules) · [neoclouds](https://www.sotkn.com/stack/neoclouds/) (who bill the hours after the module ships). Markets: [TSMC capex split](https://www.sotkn.com/markets/taiwan/taiwan-tsmc-capex-split-september-2026/) · [Chiayi packaging land](https://www.sotkn.com/markets/taiwan/taiwan-chiayi-packaging-land-october-2026/) · [Korea HBM](https://www.sotkn.com/markets/korea/korea-hbm-memory-september-2026/) · [Samsung HBM4 ask](https://www.sotkn.com/markets/korea/korea-samsung-hbm4-ask-october-2026/).

[Get the Wire](https://www.sotkn.com/#/portal/signup) — short notes when a bond or stack clock moves. Stack: [What Does TSMC Do?](https://www.sotkn.com/stack/semiconductors/cowos/what-does-tsmc-do/) · [What Does SK hynix Do?](https://www.sotkn.com/stack/semiconductors/hbm/what-does-sk-hynix-do/) · [What Does ASML Do?](https://www.sotkn.com/stack/semiconductors/what-does-asml-do/). Analysis: [where the stuck step moves](https://www.sotkn.com/analysis/where-does-the-stuck-step-move/).

**How we check this**

Figures come from company filings and company releases, each dated in the list below. Capacity and timing from press reports are labelled as reported, not guided. Where we work something out ourselves, the arithmetic is shown in full.

**Last reviewed:** 5 Oct 2026 · **Next review:** after Besi Q3 2026 results (22 Oct 2026) print hybrid-bonding orders against memory evaluations

Spot an error? [Tell us](mailto:sean@thekopinotes.com) and we will correct it and note the change here.

[Our editorial standards →](https://www.sotkn.com/editorial-standards/)

## Sources

- [Besi Q2-26 and H1-26 results — revenue €249.9m; orders €292.9m (+128.8% vs Q2-25); hybrid-bonding customers 15 → 21; Q2 hybrid-bonding orders from two repeat customers and one new hyperscaler; AI \~60% of H1 system orders; Q3 revenue +10–15%; Q3 print date 22 Oct 2026 (23 Jul 2026)](https://www.globenewswire.com/news-release/2026/07/23/3331898/0/en/be-semiconductor-industries-n-v-announces-q2-26-and-h1-26-results.html?ref=sotkn.com)
- [Besi Q2 2026 investor call — HBM hybrid bonding still in evaluation at one of three memory companies, another starting; “some are voicing that it may delay. Others are voicing that it is imminent.” Unit shipments not disclosed (23 Jul 2026)](https://www.roic.ai/quote/BESI.AS/transcripts/2026-year/2-quarter?ref=sotkn.com)
- [TSMC-SoIC — sub-10 µm bond pitch; 3 nm chip stacking entered volume production in 2025; SoIC chips can be subsequently assembled in CoWoS or SoW](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm?ref=sotkn.com)
- [TSMC 2026 North America Technology Symposium — 14-reticle CoWoS (\~10 compute dies, \~20 HBM stacks) for 2028; A14-to-A14 SoIC in 2029 with 1.8× die-to-die I/O density vs N2-on-N2 SoIC (22 Apr 2026)](https://pr.tsmc.com/system/files/newspdf/attachment/49337b40ff139d51d533076cf7a945b30e107e07/2026%20Tech%20Symposium%20%28E%29%5FFinal%5Fwmn.pdf?ref=sotkn.com)
- [TSMC Q2 2026 earnings call — packaging capacity still tight enough to limit customer growth (C.C. Wei, 16 Jul 2026)](https://investor.tsmc.com/english/encrypt/files/encrypt%5Ffile/reports/2026-07/547d1696765e05ce3adb81c108ce1c8c1682b80c/TSMC%202Q26%20Transcript.pdf?ref=sotkn.com)
- [SK hynix 2Q26 results — HBM4 mass shipments began in Q2 2026, ramp in H2; revenue 79.3187 trillion won; operating profit 60.5426 trillion won; operating margin 76% (29 Jul 2026)](https://news.skhynix.com/en/q2-2026-business-results/?ref=sotkn.com)
- [Intel Foveros Direct 3D technology brief — copper-to-copper hybrid bonding; sub-10 µm pitch; up to 10× vs conventional microbumps; Foveros 2.5D listed at 36 µm microbumps](https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/foveros-direct-3d-tech-brief.pdf?ref=sotkn.com)
- [Intel newsroom — Xeon 6+ launched as first data-centre CPU on Intel 18A; platforms with ASUS, Dell, HPE, Lenovo, Supermicro and others (1 Jun 2026)](https://newsroom.intel.com/data-center/intel-puts-agentic-ai-xeon-6-networking-ai-systems?ref=sotkn.com)
- [Intel Foundry — Clearwater Forest described as 18A compute chiplets stacked with Foveros Direct 3D onto a base die, then connected with EMIB 2.5D](https://newsroom.intel.com/intel-foundry/redefining-foundry-era-ai?ref=sotkn.com)
- [Applied Materials Kinex — integrated die-to-wafer hybrid bonding system co-developed with Besi, for advanced logic, memory, HBM and co-packaged optics](https://www.appliedmaterials.com/us/en/product-library/kinex-integrated-die-to-wafer-hybrid-bonding-system.html?ref=sotkn.com)