> ## Content Index > Fetch the complete content index at: https://www.sotkn.com/llms.txt > Use this file to discover other available public pages before exploring further. # What Is Semiconductor Yield? Why Defects Set the Price of a Chip - URL: https://www.sotkn.com/explained/semiconductor-yield-explained/ - Published: 2026-11-02T10:29:05.000Z - Updated: 2026-11-02T10:29:04.000Z - Description: Semiconductor yield is the share of chips on a wafer that work. On a standard model, the same defect rate that costs a phone chip 10% of its output costs a big AI chip more than half. Yield is capacity a fab does not have to build. - Author: Sean - Tags: Mechanism, #desk-explained EXPLAINED · Mechanism · Last reviewed: 2 Nov 2026 · Next review: after TSMC’s fourth-quarter results in January 2027 Semiconductor yield is the share of chips on a silicon wafer that come out working. A wafer holds many chips, called dies, and any die hit by a defect is usually scrapped or sold as a lower grade. **In short.** Semiconductor yield is the share of dies on a wafer that work. A fab pays the same to process a wafer whether one die works or all of them do, so yield sets the cost of every chip that ships. Big AI chips feel it most. On the standard model, the same defect rate that costs a 1 cm² phone chip about 10% of its output costs an 8 cm² AI chip more than half. Our read: yield is capacity a fab does not have to build. The foundry that learns fastest on a new node gets paid first; the stuck step is yield learning, which takes quarters and cannot be bought. Why an investor cares: a foundry is paid to run wafers, but its customer is paid for working chips. Yield is the exchange rate between the two, and on a new node it moves every quarter. Our [guide to 2nm chips](https://www.sotkn.com/explained/2nm-chip-explained/) covers the node itself; this page covers why the same wafer can be worth twice as much a year later. ## What is semiconductor yield? It is the share of chips that come out of the factory working. A 300 mm silicon wafer is printed with a grid of identical chips, called dies. After hundreds of process steps, each die is tested on the wafer. The good ones are cut out and packaged; the rest are thrown away or sold as lower-grade parts. Fabs track two kinds. Line yield is the share of wafers that make it through the factory without being scrapped for damage or a processing error. Die yield is the share of dies on a finished wafer that pass test. When people say a node has “60% yield”, they usually mean die yield for a particular chip, and that is how this page uses the word. The point for money is simple. The cost of running a wafer is fixed before anyone knows how many dies will work. Every dead die raises the cost of the ones that live. ## How is chip yield calculated? Good dies divided by all dies on the wafer. To predict it, engineers use a defect model. The simplest, taught in University of California, Berkeley course notes by Robert Leachman, assumes killer defects land at random. A die works only if none hits it, so yield equals e to the power of minus defect density times die area. Two things follow. First, defect density, written D0, is the fab’s report card: fewer defects per square centimetre means more good dies for every product. Second, the defects from each step add up. A process with more steps, or more lithography layers, has more chances to fail, which is why each new node starts with a lower yield than the one before. The model is too harsh for big chips. Real defects cluster, so some dies collect several while their neighbours stay clean, and engineers use the Murphy and negative binomial models to allow for that. The shape of the answer does not change: the bigger the die, the more it loses. ## Why do big AI chips have lower yields? Because a bigger die is a bigger target. An AI accelerator die can be eight times the area of a phone chip, close to the largest a lithography scanner can print in one shot. Each extra square centimetre is another chance for a defect to land. | Defect density (killer defects per cm²) | Phone-sized die, 1 cm² | AI-sized die, 8 cm² | | --------------------------------------- | ------------------------------------------- | ------------------------------------------ | | **0.1** (a mature process) | About 90% work; about 579 good dies a wafer | About 45% work; about 29 good dies a wafer | | **0.2** | About 82%; about 524 good dies | About 20%; about 13 good dies | | **0.5** (an early process) | About 61% | About 2% | *Second Order arithmetic on the Poisson model, yield = e−defect density × area, for a 300 mm wafer holding about 640 small or about 65 large dies (standard dies-per-wafer estimate with edge loss). Real large-die yields run higher than this because defects cluster, and designers add spare blocks so a flawed die can still ship. The direction holds: size multiplies the damage.* Our arithmetic on the simple model makes the point. At 0.1 defects per square centimetre, a 1 cm² die yields about 90% and an 8 cm² die about 45%. Double the defect rate to 0.2 and the small die loses about 10% of its output; the big die loses about 55%. For the big chip, the same wafer now produces about 2.2 times fewer working parts, so each one carries about 2.2 times the wafer cost. ![Semiconductor yield by die size and defect rate: a 1 cm² die yields about 90% at 0.1 defects per cm² while an 8 cm² AI-sized die yields about 45%, falling to about 20% at 0.2](https://storage.ghost.io/c/cd/10/cd10e222-131f-4ba4-b4a9-ca4214e8c12d/content/images/2026/11/semiconductor-yield-defect-rate-die-size-2026.png) Semiconductor yield by die size and defect rate. Poisson model; Second Order arithmetic. This is one reason AI chips are split into pieces. Several smaller dies, tested before they are joined, waste less silicon than one giant die. Our [guide to chiplets](https://www.sotkn.com/explained/chiplet-explained/) covers that trade, and our [guide to CoWoS](https://www.sotkn.com/explained/cowos-explained/) covers the packaging that joins the pieces back together. TSMC’s chief executive put it plainly on the 15 October call. New nodes used to ramp on small, simple phone chips first, which made the learning curve easier. On 2nm, small phone dies and large AI dies are ramping at the same time. He said the learning curve was there but TSMC was “doing a reasonable job”. ## Where is yield lost? At every step, and the losses multiply. Most of the attention goes to the front end, where the transistors are printed, but a chip can also die in packaging and final test. ![Semiconductor yield: where a chip can be lost, from wafer fab defects and wafer test through packaging and stacking to final test, with the wafer fab as the stuck step](https://storage.ghost.io/c/cd/10/cd10e222-131f-4ba4-b4a9-ca4214e8c12d/content/images/2026/11/semiconductor-yield-where-chips-are-lost.png) Where semiconductor yield is lost. Second Order. High-bandwidth memory shows why the back end matters. An HBM4 stack is twelve or more memory dies bonded on top of a base die. Even if every die tested good, each bond is another chance to fail. Our arithmetic, for illustration only: if each of twelve bonding steps succeeds 99% of the time, about 89% of stacks survive; at 98% about 79%; at 95% only about 54%. That is why SK hynix was careful with its words on 28 October. It said its back-end yield is measured across the whole process, not step by step through bumping, stacking and final test, and that HBM4 had beaten its planned yield, so the target was raised. Our [Analysis on the HBM4 back end](https://www.sotkn.com/analysis/sk-hynix-hbm4-back-end-stuck-step-what-price-assumes/) works through the cash side, and our [Players page on who tests AI chips](https://www.sotkn.com/explained/who-tests-ai-chips/) covers the companies that catch the failures. ## What yields are TSMC, Intel and Samsung getting in 2026? Nobody says. Companies describe yield in words and almost never give a number. The figures that circulate come from the press and analysts, and should be read that way. | Company and process | What it said or what was reported | Status | | ---------------------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ------------------------------------------------------ | | **TSMC, N2 (2nm)** | In volume production since the fourth quarter of 2025 “with good yield”; 8% of wafer revenue in the third quarter of 2026\. Reported in the high 60s in April 2026 | Company words, no figure; the number is a press report | | **Intel, 18A** | Yields rising at a double-digit rate and at “industry standard levels”; 18A costs down about 40% since the first quarter. Reported in the low 50s in April 2026 | Company words, no figure; the number is a press report | | **Samsung, SF2 (2nm)** | Reported at 20–30% in the second half of 2025, about 55% in April 2026 and about 60% by late September 2026; volume production began in the third quarter with hyperscaler orders | Press reports; Samsung gave no figure | | **SK hynix, HBM4** | Back-end yield, measured across the whole process, above plan, so the target was raised | Company words, no figure | *Company statements from results and calls dated 15 to 29 October 2026; reported figures from Electronics Weekly (15 April 2026) and Tech Times (30 October 2026). Yield numbers for leading-edge nodes are almost never disclosed, so read every percentage here as reported, not confirmed.* Intel’s numbers show what rising yield does even without a percentage. Its finance chief said 18A costs fell about 40% between the first and third quarters of 2026 and Intel 3 costs about 15%, driven by higher yields, faster cycle times and fuller factories. Our arithmetic: a 40% cost cut means the same spend now makes about 1.67 times as many 18A units. Samsung’s reported path is steeper. From 20–30% in the second half of 2025 to about 60% by late September 2026, on press reports. Our arithmetic, taking 25% as the starting midpoint: the same wafer now gives about 2.4 times as many good chips, and the cost of each good chip falls by about 58%. On 29 October Samsung said it was still winning 2nm orders from high-performance computing customers, including major hyperscalers. Our [Markets note on Samsung’s HBM4 yield](https://www.sotkn.com/markets/korea/korea-samsung-hbm4-yield/) covers the memory side of the same story. ## Who gets paid when yields rise? Our read: the foundry that learns fastest is paid first, its customer next, and the equipment makers keep getting paid either way. - **The foundry, through margin.** A new node dilutes margin until yields climb. TSMC’s gross margin fell 1.3 points to 66.4% in the third quarter on its 2nm ramp, and it guided 66% for the fourth. Our arithmetic: that is about 1.7 points below the second quarter’s 67.7%. As 2nm yields rise, that drag shrinks. - **The chip designer, through cost per chip.** Under a price-per-wafer deal, the designer pays for dead dies too. Every point of yield the foundry gains lowers the designer’s cost per working chip without a price cut. - **The equipment and test makers, through volume.** Inspection, metrology and test tools are how yield is found and fixed. Their customers buy more of them on a new node, whatever the yield is that quarter. The less obvious point is capacity. Our arithmetic: lifting yield from 60% to 80% gives about 33% more working chips from the same wafers, the same tools and the same cleanroom. Today’s [Markets note on Taiwan’s ready fab shells](https://www.sotkn.com/markets/taiwan/taiwan-ready-fab-shell-capex-november-2026/) shows how long it takes to add floor space. Yield is the one source of extra output that does not wait for a building. ## Where is the stuck step? Our read: yield learning. A fab cannot buy a lower defect rate. It has to run wafers, find where each defect comes from, change the process and run more wafers to check the fix. Each turn takes weeks, because a wafer spends months moving through the line. The clocks are long. TSMC’s 2nm has been in volume production since the fourth quarter of 2025 and was still diluting margin a year later. Samsung’s reported climb from 20–30% to about 60% took about a year. Our [guide to clean rooms](https://www.sotkn.com/explained/clean-room-explained/) and [Players page on who makes wafer fab equipment](https://www.sotkn.com/explained/who-makes-wafer-fab-equipment/) cover the factory side of the same clock. ## Why does yield matter for Taiwan and Korea? Because that is where most leading-edge yield is learned. TSMC is ramping 2nm in Hsinchu and Kaohsiung and says it expects 2nm-family capacity to more than double in 2027\. Korea’s memory makers carry the HBM stacking risk. Our [Markets note on SK hynix’s third quarter](https://www.sotkn.com/markets/korea/korea-sk-hynix-q3-hbm4-october-2026/) and [Wire on TSMC’s 2nm share of revenue](https://www.sotkn.com/wire/tsmc-q3-2026-2nm-8-percent-demand-above-supply-wire/) track both. ## What would change the view? - **A company publishes numbers.** If TSMC, Samsung or Intel discloses defect density or die yield, the reported figures here would give way to real ones. - **Margins stop recovering.** If TSMC’s 2nm dilution does not narrow through 2027, yield learning is slower than the company says. - **Back-end yields slip.** If taller HBM stacks or larger packages lose more parts at the bonding step, the stuck step moves from the fab to packaging. ## Common misconceptions - **People assume yield is a fixed property of a node.** Actually it depends on the chip. The same process can yield about 90% on a small die and well under half on a large one. - **People assume a failed die is wasted money only for the fab.** Actually, under a price-per-wafer contract, the customer pays for the dead dies too. - **People assume companies publish their yields.** Actually they almost never do. Most yield percentages in the news are reports, not disclosures. - **People assume yield ends at the wafer.** Actually packaging and stacking add their own losses, and a failure there throws away good dies too. ## FAQ **What is semiconductor yield?** Semiconductor yield is the share of chips on a wafer that work. If a wafer holds 100 dies and 80 pass testing, the die yield is 80%. Fabs also track line yield, the share of wafers that survive the process without being scrapped. **How is chip yield calculated?** Good dies divided by total dies on the wafer. The simplest model links it to defect density and die size: yield equals e to the power of minus defect density times die area. At 0.1 defects per square centimetre, a 1 cm² die yields about 90% on that model. **Why do big AI chips have lower yields?** Because a bigger die is a bigger target. Each die works only if no killer defect lands on it, so the chance of a clean die falls as area rises. On the simple model, a die eight times larger yields about 45% where a small one yields about 90%, at the same defect rate. **What is a good yield for a new chip process?** There is no published standard, and companies rarely disclose figures. Reports in 2026 put Samsung’s 2nm near 60% and TSMC’s 2nm in the 60s, and said many chip designers want about 70% before committing high volumes. Treat these as reported, not company figures. **Who pays when yields are low?** It depends on the contract. When a foundry sells by the wafer, the customer pays for the dead dies too. When a deal prices by good die, the foundry carries the loss. Either way, low yield shows up as a higher cost per working chip. **What is HBM stack yield?** It is the share of high-bandwidth memory stacks that work after many memory dies are bonded on top of each other. Every bonding step can fail, so the losses multiply. SK hynix said in October 2026 that it measures back-end yield across the whole process, not step by step. **Is this a list of stocks to buy or sell?** No. This page explains semiconductor yield and where it binds. It does not rank companies or give buy or sell calls. Not investment advice. Do your own research. Related: [2nm chip](https://www.sotkn.com/explained/2nm-chip-explained/); [chiplet](https://www.sotkn.com/explained/chiplet-explained/); [HBM](https://www.sotkn.com/explained/hbm-explained/); [CoWoS](https://www.sotkn.com/explained/cowos-explained/); [clean room](https://www.sotkn.com/explained/clean-room-explained/). ## Stack doors Layer: [Semiconductors](https://www.sotkn.com/stack/semiconductors/). Markets: [Taiwan](https://www.sotkn.com/markets/taiwan/), [Korea](https://www.sotkn.com/markets/korea/), [US](https://www.sotkn.com/markets/us/). [Get the Wire](https://www.sotkn.com/#/portal/signup) — short daily notes when yields, nodes and margins move. Not investment advice. Do your own research. **How we check this** TSMC’s yield wording, margins and 2nm revenue share come from its earnings call of 15 October 2026\. Intel’s yield wording and cost declines come from its earnings call of 29 October 2026\. SK hynix’s HBM yield wording comes from its call of 28 October 2026, and Samsung’s foundry orders from its results release of 29 October 2026\. The reported yield percentages come from Electronics Weekly on 15 April 2026 and Tech Times on 30 October 2026; no company confirmed them, and we label them as reported. The yield model comes from Robert Leachman’s University of California, Berkeley course notes. The model yields, dies per wafer, good-die counts, stack-yield examples, margin differences and cost ratios are our arithmetic, checked in code and labelled as ours on the page. The order of who gets paid and the stuck step are our read. The featured photograph is credited in its caption. This page explains semiconductor yield. It does not rank companies or give buy or sell calls. Not investment advice. Do your own research. **Last reviewed:** 2 Nov 2026 · **Next review:** after TSMC’s fourth-quarter results in January 2027 Spot an error? [Tell us](mailto:sean@thekopinotes.com) and we will correct it and note the change here. [Our editorial standards →](https://www.sotkn.com/editorial-standards/) ## References 1. [TSMC — third-quarter 2026 earnings call transcript (15 Oct 2026)](https://investor.tsmc.com/english/encrypt/files/encrypt%5Ffile/reports/2026-10/eba4fac72873bf546b669bd2b5d973df5c93215d/TSMC%203Q26%20Transcript.pdf?ref=sotkn.com) — N2 in volume production since the fourth quarter of 2025 “with good yield”; gross margin 66.4%, down 1.3 points on 2nm ramp dilution; fourth-quarter guide 66% at the midpoint; N2 8% of wafer revenue; yield learning with big and small dies at once 2. [Intel — third-quarter 2026 earnings call transcript, via The Motley Fool (29 Oct 2026)](https://www.fool.com/earnings/call-transcripts/2026/10/30/intel-intc-q3-2026-earnings-call-transcript/?ref=sotkn.com) — 18A yields improving at a double-digit rate and at “industry standard levels”; 18A costs down about 40% and Intel 3 about 15% since the first quarter; higher yields, cycle times and utilisation cutting wafer costs; no yield figure given 3. [SK hynix — third-quarter 2026 earnings call transcript, via The Motley Fool (28 Oct 2026)](https://www.fool.com/earnings/call-transcripts/2026/10/28/sk-hynix-skhy-q3-2026-earnings-call-transcript/?ref=sotkn.com) — back-end yield measured across the whole process, not single steps such as bump, stack or final test; HBM4 above planned yield and target raised; HBM3E above planned mature yield 4. [Samsung Electronics — third-quarter 2026 results (29 Oct 2026)](https://news.samsung.com/global/samsung-electronics-announces-third-quarter-2026-results?ref=sotkn.com) — foundry revenue and earnings improved on HBM base-die sales and advanced-node sales; continued 2nm order wins from HPC customers including major hyperscalers; no yield figure 5. [Tech Times — Samsung Foundry confirms hyperscaler 2nm orders as first GAA chips enter production (30 Oct 2026)](https://www.techtimes.com/articles/329716/20261030/samsung-foundry-confirms-hyperscaler-2nm-orders-first-gaa-chips-enter-production.htm?ref=sotkn.com) — reported Samsung 2nm front-end yield of about 60% by late September 2026, from below 20% in late 2025; reported 70% bar many chip designers want before high-volume commitments 6. [Electronics Weekly — Samsung 2nm yields inch towards mass production (15 Apr 2026)](https://www.electronicsweekly.com/news/business/sam-sung-inches-towards-mass-production-yields-2026-04/?ref=sotkn.com) — reported Samsung 2nm yield around 55%, from 20–30% in the second half of 2025 (TrendForce, citing Busan Ilbo); TSMC 2nm reported in the high 60s and Intel 18A in the low 50s 7. [Robert C. Leachman, University of California, Berkeley — Yield Modeling and Analysis, IEOR 130 course notes (Spring 2014)](https://fog.misty.com/perry/cod/references/yield%5Fmodels.pdf?ref=sotkn.com) — line yield vs die yield; Poisson die-yield model (yield = e to the minus defect density times die area); defects add up across steps; clustering makes Poisson pessimistic for large dies, hence the Murphy and negative binomial models S **[Sean](https://www.sotkn.com/author/sean/)** Writes Second Order by TKN — a plain-English map of AI infrastructure and semiconductors for non-specialist investors. Focus: who gets paid, where money sticks, and which step is stuck. Covers AI infrastructure, semiconductors, and second-order stack reads. [Author page →](https://www.sotkn.com/author/sean/) · [Editorial standards →](https://www.sotkn.com/editorial-standards/)