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# SoIC vs CoWoS: Height Versus Width — and Who Still Waits
- URL: https://www.sotkn.com/explained/soic-vs-cowos/
- Published: 2026-10-29T01:13:57.000Z
- Updated: 2026-10-29T01:13:57.000Z
- Description: SoIC stacks chips; CoWoS sits them beside HBM. TSMC sells both. The stuck step for a shippable AI GPU is still the CoWoS slot, not the 3D join.
- Author: Sean
- Tags: #desk-explained, Versus

EXPLAINED · Versus · Last reviewed: 29 Oct 2026 · Next review: after TSMC reports fourth-quarter 2026 results

SoIC is TSMC’s wafer-level way of stacking finished chips on top of one another so they behave like one piece of silicon. CoWoS is TSMC’s way of sitting those chips — and the high-bandwidth memory they still need — side by side on a shared base, then onto a substrate, so an AI accelerator can ship as one module.

**In short.** SoIC is height. CoWoS is width. TSMC calls SoIC the frontend 3D stacking service and CoWoS the backend package that enlarges the envelope so more compute and more HBM fit in one module. The stacked chip is then assembled with CoWoS; it is not a substitute for the interposer that still holds HBM. On 15 October 2026 TSMC’s chairman said CoWoS is still customers’ number-one choice, that 5×-reticle packages are in real-world production, and that the back end is still a little short. Our read: the 3D join is in volume for logic-on-logic. The stuck step for a shippable AI GPU is still the CoWoS slot.

The two names get used as if one will retire the other. They do not. Our [SoIC explainer](https://www.sotkn.com/explained/soic-explained/) covers the vertical join; our [CoWoS explainer](https://www.sotkn.com/explained/cowos-explained/) covers the lateral one. This page is the cash split: who gets paid for stacking, who gets paid for spreading, and which clock still binds the finished module.

## What is the difference between SoIC and CoWoS?

Height versus width. SoIC stacks known-good dies on top of one another at a bond pitch that starts below 10 micrometres, so the result looks like one SoC from the outside. CoWoS — chip-on-wafer-on-substrate — places logic and HBM beside each other on an interposer-class base, then onto a substrate. One adds a floor. The other adds a street.

TSMC’s SoIC page says the stacked chip can then be assembled with CoWoS or TSMC-SoW. 3-nanometre SoIC stacking entered volume production in 2025\. CoWoS has been in volume since 2012.

|                         | SoIC                                                        | CoWoS                                                            |
| ----------------------- | ----------------------------------------------------------- | ---------------------------------------------------------------- |
| **What it is**          | Wafer-level 3D stacking of finished chips                   | 2.5D packaging: chips and HBM on a shared base, then a substrate |
| **Direction**           | Vertical                                                    | Lateral                                                          |
| **TSMC’s own label**    | Frontend 3D stacking                                        | Backend advanced packaging                                       |
| **Join**                | Copper-to-copper hybrid bond, sub-10µm pitch                | Silicon interposer, organic RDL, or local silicon interconnects  |
| **What it holds today** | Logic on logic (cache, I/O, compute chiplets)               | Compute plus HBM, side by side                                   |
| **Volume date (TSMC)**  | 3nm stacking from 2025; A14-to-A14 set for 2029             | Family since 2012; 5× / 5.5× reticle in production in 2026       |
| **What it does not do** | Does not, in production AI GPUs, put HBM on the compute die | Does not stack dies on top of each other; that is SoIC’s job     |

*TSMC SoIC, CoWoS and HPC 3DFabric pages; TSMC 22 April 2026 symposium release; 15 October 2026 earnings call.*

Hybrid bonding is the copper join inside SoIC. It is not a third packaging family. Our [hybrid bonding explainer](https://www.sotkn.com/explained/hybrid-bonding-explained/) is the physics; SoIC is TSMC’s manufacturing wrapper around it. CoWoS vs Intel’s EMIB is a different comparison — two ways to do the lateral join — and lives on [CoWoS vs EMIB](https://www.sotkn.com/explained/cowos-vs-emib/).

## How do they sit in TSMC's 3DFabric?

As a pair, not as rivals. 3DFabric is TSMC’s family name for frontend stacking and backend packaging together: SoIC, CoWoS and InFO. The HPC platform page says frontend SoIC supports chiplet stacking at the chip level, and that backend 3D stacking “increases the envelope size and enriches CoWoS technical contents” so more compute and more memory bandwidth fit the same module.

That is why TSMC can sell both on one accelerator. AMD’s CDNA 3 white paper is the production example: up to eight accelerator complex dies stacked on four I/O dies, with eight HBM3 stacks still sitting beside them. The XCDs are on TSMC 5-nanometre; the I/O dies are on 6-nanometre. Instinct MI300X carries 192 GB of HBM3 at 5.3 TB/s peak — all of it around the stack, not on it. The shorthand for using both is 3.5D.

NVIDIA’s Blackwell architecture page describes a different lateral pattern: two reticle-limited dies connected at 10 terabytes per second on a custom TSMC 4NP process. That page does not name SoIC. Reuters reported Jensen Huang saying Blackwell would use largely CoWoS-L — reported, not an NVIDIA filing.

CoWoS itself is three variants, which is why a “CoWoS slot” headline can mean the wrong line:

| Variant | Base                                                                    | Why it matters                                       |
| ------- | ----------------------------------------------------------------------- | ---------------------------------------------------- |
| CoWoS-S | Silicon interposer up to about 3.3× reticle (\~2,700 mm²)               | Highest-density classic route; Hopper-class packages |
| CoWoS-R | Organic RDL interposer                                                  | Easier to scale; lower density than silicon          |
| CoWoS-L | RDL plus local silicon interconnects; 3.5× reticle in volume since 2024 | Route for very large multi-die AI packages           |

TSMC recommends CoWoS-L or CoWoS-R when the interposer needs to exceed the CoWoS-S size band. SoIC does not replace any of the three. It can sit on whichever variant the designer picked, as one SoC-like chip among the others on the interposer.

## When does a designer use SoIC, CoWoS, or both?

SoIC when two pieces of logic need to behave as one die: a cache on a CPU, compute on I/O, or a photonic engine on a compute stack. TSMC lists heterogeneous known-good dies of different sizes, functions and nodes, Gen-2 for N2 and beyond, and COUPE for silicon photonics. A14-to-A14 SoIC is dated 2029, at 1.8 times the die-to-die I/O density of N2-on-N2 SoIC.

CoWoS when the part has to talk to HBM. Memory stacks from SK hynix, Samsung and Micron still sit beside the compute. TSMC’s April 2026 release said it is producing 5.5-reticle CoWoS, with a 14-reticle version — about 10 large compute dies and 20 HBM stacks — slated for 2028, then beyond 14 reticles in 2029\. On the 15 October 2026 call, C.C. Wei said TSMC is in real-world production of 5×-reticle packages, working on 9× and then 14×. CoWoS is still customers’ number-one choice; CoPoS is a later cost-reduction path.

Both when the designer wants more logic in the same footprint *and* still needs the HBM only the interposer holds. That is today’s AI package. If SoIC were going to retire CoWoS, TSMC would not be stretching the interposer toward 14 reticles while dating A14-to-A14 SoIC to 2029.

Our arithmetic, illustration not forecast: 20 HBM stacks on the 2028 14-reticle outline is 2.5 times the eight stacks on MI300X — a 12-stack increase per module. TSMC is still multiplying the beside number.

## Who gets paid — and where is the stuck step?

Four groups of cash.

TSMC is paid twice when a part uses both: once for the SoIC stack, once for the CoWoS (or InFO, or SoW) that wraps it. SoIC is an extra process step on the same campus, not a second-vendor bake-off. On the 15 October 2026 call Wei said TSMC is building 13 leading-edge and advanced-packaging fabs in Taiwan over the next several years, plus five to six overseas, and that demand is still “far above our capability today to supply.” He also said there is “a little bit shortage on the back end,” which is why TSMC designed a deal with GlobalFoundries for silicon interposers.

Bonding-tool makers are paid as logic stacking ramps. Memory makers — SK hynix, Samsung, Micron — are still paid for the HBM around the edge. Our [HBM explainer](https://www.sotkn.com/explained/hbm-explained/) is that neighbour clock. Chip designers are paid for the accelerator: AMD already ships the 3.5D pattern; NVIDIA’s public Blackwell language is two dies and a 10 TB/s link, a CoWoS-scale lateral problem.

The stuck step is the CoWoS slot, not the SoIC join. Logic-on-logic stacking is in volume. The package that places HBM beside the die is the one Wei still calls a little short, still customers’ first choice, and still without a company wafers-per-month figure. We will not borrow a secondhand capacity number. A billed leading-edge wafer is not a finished module. Our [Taiwan TSMC Q3 pulse](https://www.sotkn.com/markets/taiwan/taiwan-tsmc-q3-cowos-october-2026/) is the wafer receipt on the same 15 October print: US$46.72 billion of sales is not a CoWoS-volume print.

Our read: TSMC gets paid for height and for width. Cash still sticks on width. SoIC adds a third dimension of logic. It does not move AI memory off the interposer, and it does not open a CoWoS slot.

## What would change the view?

- Memory-on-logic names a customer. A GPU or ASIC that ships with DRAM on the compute die turns the vertical path into the bind, and CoWoS reticle size would matter less.
- CoWoS 14-reticle slips, or Wei stops calling the back end short. Designers would wait, or pull more bandwidth into a vertical stack sooner.
- SoIC A14-to-A14 slips past 2029\. More of the AI package’s scaling would stay on CoWoS and on larger HBM stacks.
- A second packager qualifies volume on a leading AI accelerator. The CoWoS brand would then share the stuck step, not retire it.

## Common misconceptions

- People assume SoIC replaces CoWoS. Actually TSMC sells them as a pair. SoIC makes a taller chip; CoWoS makes a wider module that still holds HBM.
- People assume SoIC is hybrid bonding. Actually hybrid bonding is the join. SoIC is TSMC’s process and service that uses that join, plus known-good-die flow and TSVs, and then hands the stack to a package.
- People assume HBM already sits on the GPU. Actually production AI packages still place HBM beside the compute die on CoWoS. AMD’s MI300X is the 3.5D proof: stacked logic, memory around the edge.
- People assume a 5×-reticle print means the packaging gate has cleared. Actually Wei said CoWoS is still the first choice, 9× and 14× are still in work, and the back end is still a little short.

## FAQ

**What is the difference between SoIC and CoWoS?**  
SoIC stacks chips vertically so they behave like one SoC. CoWoS places chips and high-bandwidth memory side by side on an interposer, then onto a substrate. TSMC calls SoIC a frontend 3D stacking service and CoWoS a backend packaging service; an AI accelerator can use both.

**Does SoIC replace CoWoS?**  
No. TSMC’s SoIC page says the stacked chip can then be assembled with CoWoS or System-on-Wafer. TSMC is stretching CoWoS toward a 14-reticle package in 2028, which is not what a replacement looks like.

**How is SoIC different from hybrid bonding?**  
Hybrid bonding is the copper-to-copper join. SoIC is TSMC’s manufacturing service that uses that join, plus through-silicon vias and known-good-die handling, to make a 3D stack that can drop into CoWoS or InFO.

**Why does an AI GPU still need CoWoS if it uses SoIC?**  
Because production HBM still sits beside the compute die, not on it. SoIC can stack cache or I/O today. The memory stacks that feed an AI GPU still need the lateral package. That is why AMD’s MI300X stacks logic and still carries eight HBM cubes around the edge.

**Who gets paid for SoIC versus CoWoS?**  
TSMC is paid for both when a part uses both. Memory makers are paid for the HBM on the CoWoS interposer. Bonding-tool makers are paid as logic stacking ramps. The designer is paid for the finished accelerator. The scarce invoice is still the CoWoS slot.

**Is this a list of stocks to buy or sell?**  
No. This page explains how SoIC and CoWoS differ and where the money goes. It does not rank companies or give buy or sell calls. Not investment advice. Do your own research.

## Related terms

Related: [SoIC](https://www.sotkn.com/explained/soic-explained/); [CoWoS](https://www.sotkn.com/explained/cowos-explained/); [CoWoS vs EMIB](https://www.sotkn.com/explained/cowos-vs-emib/); [hybrid bonding](https://www.sotkn.com/explained/hybrid-bonding-explained/); [interposer](https://www.sotkn.com/explained/interposer-explained/); [chiplet](https://www.sotkn.com/explained/chiplet-explained/); [HBM](https://www.sotkn.com/explained/hbm-explained/); [who makes advanced packaging](https://www.sotkn.com/explained/who-makes-advanced-packaging/).

## Markets and stack doors

Layer: [Semiconductors](https://www.sotkn.com/stack/semiconductors/). Also: [CoWoS hub](https://www.sotkn.com/stack/semiconductors/cowos/) and [What TSMC does](https://www.sotkn.com/stack/semiconductors/what-does-tsmc-do/). Markets: [Taiwan](https://www.sotkn.com/markets/taiwan/) and [TSMC’s Q3 CoWoS pulse](https://www.sotkn.com/markets/taiwan/taiwan-tsmc-q3-cowos-october-2026/).

[Get the Wire](https://www.sotkn.com/#/portal/signup) — short daily notes when packaging, HBM and AI capacity move.

Not investment advice. Do your own research.

**How we check this**

Definitions come from TSMC’s SoIC, CoWoS and HPC 3DFabric pages and the 22 April 2026 symposium release. The 15 October 2026 packaging language comes from TSMC’s Q3 earnings call. MI300X comes from AMD’s CDNA 3 white paper and product page. NVIDIA’s two-die description is from NVIDIA’s architecture page; the CoWoS-L quote is Reuters reporting Huang, labelled reported. The 2.5-times and 12-stack multiples are our arithmetic on TSMC’s 14-reticle outline versus AMD’s eight HBM stacks. We do not use secondhand wafer-start estimates. Where we interpret, it is labelled “our read”. Not investment advice. Do your own research.

**Last reviewed:** 29 Oct 2026 · **Next review:** after TSMC reports fourth-quarter 2026 results

Spot an error? [Tell us](mailto:sean@thekopinotes.com) and we will correct it and note the change here.

[Our editorial standards →](https://www.sotkn.com/editorial-standards/)

## Sources

1. [TSMC — TSMC-SoIC (3DFabric technology page)](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm?ref=sotkn.com) — wafer-level 3D stacking; sub-10µm pitch; 3nm stacking in volume from 2025; then CoWoS or SoW
2. [TSMC — CoWoS (3DFabric technology page)](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm?ref=sotkn.com) — CoWoS-S up to 3.3× reticle (\~2,700 mm²); CoWoS-L or -R above that; CoWoS-L 3.5× in volume since 2024; family in production since 2012
3. [TSMC — HPC Platform, TSMC 3DFabric](https://www.tsmc.com/english/dedicatedFoundry/technology/platform%5FHPC%5Ftech%5FWLSI?ref=sotkn.com) — SoIC as frontend 3D stacking; CoWoS as backend; 5.5×-reticle CoWoS certified in 2025, volume production in 2026
4. [TSMC — Debuts A13 Technology at 2026 North America Technology Symposium (22 Apr 2026)](https://pr.tsmc.com/english/news/3302?ref=sotkn.com) — producing 5.5-reticle CoWoS; 14-reticle CoWoS (\~10 compute dies, 20 HBM) for 2028; A14-to-A14 SoIC for 2029 at 1.8× I/O density vs N2-on-N2
5. [TSMC — Reports Third Quarter EPS of NT$29.43 (15 Oct 2026)](https://pr.tsmc.com/english/news/3346?ref=sotkn.com) — Q3 sales NT$1,494.24bn / US$46.72bn
6. [TSMC — Q3 2026 earnings-call transcript (15 Oct 2026)](https://investor.tsmc.com/english/encrypt/files/encrypt%5Ffile/reports/2026-10/eba4fac72873bf546b669bd2b5d973df5c93215d/TSMC%203Q26%20Transcript.pdf?ref=sotkn.com) — 5× reticle in real-world production; CoWoS still number-one choice; 9× then 14× in work; back end a little short; GlobalFoundries interposers; demand far above supply
7. [AMD — CDNA 3 architecture white paper](https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/white-papers/amd-cdna-3-white-paper.pdf?ref=sotkn.com) — up to eight vertically stacked accelerator dies and four I/O dies, plus eight HBM stacks; XCDs on TSMC 5nm, IODs on TSMC 6nm
8. [AMD — Instinct MI300X product page](https://www.amd.com/en/products/accelerators/instinct/mi300/mi300x.html?ref=sotkn.com) — 192 GB HBM3, 5.3 TB/s peak
9. [NVIDIA — Blackwell architecture](https://www.nvidia.com/en-us/data-center/technologies/blackwell-architecture/?ref=sotkn.com) — two reticle-limited dies, 10 TB/s chip-to-chip interconnect, custom TSMC 4NP process
10. [Reuters — Nvidia CEO says its advanced packaging technology needs are changing (16 Jan 2025)](https://www.reuters.com/technology/nvidia-ceo-says-its-advanced-packaging-technology-needs-are-changing-2025-01-16/?ref=sotkn.com) — reported: Huang said Blackwell would use largely CoWoS-L, Hopper CoWoS-S