> ## Content Index > Fetch the complete content index at: https://www.sotkn.com/llms.txt > Use this file to discover other available public pages before exploring further. # Who Tests AI Chips? Testers, Probe Cards and Test Houses - URL: https://www.sotkn.com/explained/who-tests-ai-chips/ - Published: 2026-10-28T10:27:28.000Z - Updated: 2026-10-28T10:27:27.000Z - Description: AI chips are tested by four kinds of company: tester makers, probe card and interface makers, outsourced test houses, and foundries and chip firms with their own floors. Longer tests per chip make tester time the stuck step. - Author: Sean - Tags: Players, #desk-explained EXPLAINED · Players · Last reviewed: 28 Oct 2026 · Next review: after KYEC’s October 2026 revenue (early November) and Advantest’s next results AI chips are tested by four kinds of company: tester makers, probe card and interface makers, outsourced test houses, and the foundries and chip firms that run their own test floors. **In short.** Four kinds of company test AI chips. Tester makers such as Advantest and Teradyne build the machines. Probe card and interface makers such as FormFactor build the parts that touch each chip. Test houses such as KYEC, ASE and Amkor run the test floors for others. Foundries and chip firms run some test themselves. Each new AI chip spends longer on the tester: about four times Hopper’s final test time for Blackwell and about seven times for Rubin, on a Nomura estimate. Our read: the stuck step is tester time, so the money goes first to whoever sells the machines and then to whoever owns the hours. Why an investor cares: a finished AI chip cannot be sold until it passes test, and each generation needs more time on the tester than the last. That moves money to the companies that make the testers and own the hours, and it can hold back shipments even when wafers and packages are ready. Our [guide to who makes advanced packaging](https://www.sotkn.com/explained/who-makes-advanced-packaging/) covers the step just before test; this page covers the checks that decide whether the chip ships. ## Who tests AI chips? Four kinds of company, and most AI chips pass through more than one of them. A tester maker builds the machine, a probe card maker builds the part that touches the chip, a test house or the chipmaker itself runs the floor, and the chip designer pays for all of it. The table sets out each role. | Role | Examples | How they get paid | What they wait on | | ---------------------------------- | --------------------------------------------------- | ------------------------------------------------------------------------ | ----------------------------------------------------------------------------------------------------- | | **1\. Tester makers** | Advantest, Teradyne | Sale of each automated test system, then service on the installed base | Their own build capacity and parts; Advantest aims to go from over 5,000 to 10,000 SoC testers a year | | **2\. Probe cards and interfaces** | FormFactor, Technoprobe; Advantest interface boards | A new card or board for each chip design, then replacements as they wear | New chip designs reaching volume | | **3\. Test houses** | KYEC, ASE, Amkor | Fees per test hour or per chip; now also advances from big customers | Testers delivered and floor space ready | | **4\. In-house test** | Foundries, chip firms, memory makers | Not paid as a service: test is a cost inside the chip price | The same testers, from the same two makers | *Roles, not a ranking. Some companies play two roles: Advantest sells testers and interface boards, and Amkor packages chips as well as testing them.* The roles meet at one machine. Every chip, whoever designed it, is checked on an automated tester, and the testers that check AI processors come mainly from two companies. That is why the first two rows of the table matter for everyone below them. Our [guide to who makes AI chips](https://www.sotkn.com/explained/who-makes-ai-chips/) covers the designers who pay the bill. ## What does AI chip testing involve? Testing happens at least twice. Wafer sort checks each chip while it is still on the wafer, through a probe card whose needles touch the chip’s pads. Final test checks the chip again after it has been packaged, often followed by burn-in, where chips run under heat and voltage stress, and system-level test, where the chip runs real software on a board. Amkor’s quarterly filing lists that sequence as the services it sells: wafer probe, packaging, burn-in, system-level and final test. For an AI accelerator the package holds a large compute die, several stacks of high-bandwidth memory and thousands of connections, and each part has to be checked before an expensive module leaves the plant. Our read: testing before packaging matters more as packages get bigger, because one bad die can scrap a whole package of good memory. That is the logic behind [chiplets](https://www.sotkn.com/explained/chiplet-explained/) and stacked [HBM](https://www.sotkn.com/explained/hbm-explained/), and it is why each new design adds test steps rather than removing them. ![Who tests AI chips: estimated final test time per NVIDIA AI chip, Hopper 1x, Blackwell about 4x, Rubin about 7x](https://storage.ghost.io/c/cd/10/cd10e222-131f-4ba4-b4a9-ca4214e8c12d/content/images/2026/10/ai-chip-final-test-time.png) Estimated final test time per chip, Hopper = 1\. Nomura estimate via Seoul Economic Daily, as carried by TrendForce News, 27 Oct 2026. ## Why is AI chip testing taking longer? Because each generation puts more into one package. Nomura estimates, as reported by Seoul Economic Daily and carried by TrendForce News on 27 October 2026, that NVIDIA’s Blackwell takes about four times as long as Hopper in final test, and Rubin about seven times as long. These are analyst estimates, not NVIDIA figures. Advantest makes the same point in its own words. In its results on 28 October 2026 it said tester demand is driven by rising chip volumes, along with more test content and more test insertions with each new generation, and that demand now spans GPUs, custom chips, CPUs and high-performance memory. Our arithmetic: if a Rubin chip spends seven times as long in final test as a Hopper chip did, one tester running the same number of chips at once handles about one-seventh as many Rubin chips an hour. More packaging lines do not fix that. The floor also needs more testers, more probe cards and sockets, and more space. ## Who makes semiconductor test equipment? The machines come mainly from Advantest of Japan and Teradyne of the US. Both reported this week, and both are growing fast on AI work. | Company | Latest figure | What it shows | | ------------------------------------- | --------------------------------------------------------------------------------------------------------------------------- | ------------------------------------------------------- | | **Advantest**, quarter to 30 Sep 2026 | SoC test system sales ¥353.3B, memory test system sales ¥53.4B; full-year sales forecast raised to ¥1,863.0B from ¥1,714.0B | Processor testers are most of the business | | **Teradyne**, quarter to 27 Sep 2026 | Revenue $1,306M against $769M a year earlier; Semiconductor Test $1,072M; fourth-quarter guide $1,250–1,350M | Memory and system test are setting records on AI demand | | **SEMI forecast**, 14 Jul 2026 | Test equipment sales up 31.0% to $15.3B in 2026, $20.8B in 2028; assembly and packaging equipment $6.7B in 2026 | More is spent on test tools than on packaging tools | *From each company’s results release or presentation, and SEMI’s forecast, on the dates shown.* Advantest’s July–September quarter brought ¥353.3 billion of SoC test system sales, the testers used for processors, against ¥53.4 billion of memory testers. Its first-half sales were ¥845.2 billion, up 60.5%, and it raised its full-year forecast to ¥1,863.0 billion. It expects the 2026 market for SoC testers to reach about $11.5 billion, near the top of its range, and said supply constraints in chips and advanced packaging should last into 2027. Teradyne’s third-quarter revenue was $1,306 million, up 70% from $769 million a year earlier, and $1,072 million of it came from Semiconductor Test. Our arithmetic: that is about 82% of the total. It reported record revenue in memory test and in its integrated systems test unit, and guided the fourth quarter to $1,250 million to $1,350 million. SEMI, the industry association, put the whole test equipment market at $15.3 billion for 2026 in its July forecast, up 31.0% after a 55.3% jump in 2025, rising to $20.8 billion by 2028\. Our arithmetic: that is more than twice the $6.7 billion forecast for assembly and packaging equipment. Our [guide to wafer fab equipment](https://www.sotkn.com/explained/who-makes-wafer-fab-equipment/) covers the much larger market for the tools that make the chips in the first place. ## What do probe cards and test interfaces do? A probe card carries the tester’s signals to the chip. It holds hundreds or thousands of fine needles or micro-springs that touch each chip’s pads during wafer sort; at final test, a socket and interface board do the same job for the packaged chip. Each new chip design needs its own card or board, and they wear out with use. FormFactor is a US maker of probe cards and probe systems. On 12 October 2026 Teradyne agreed to make a $300 million strategic equity investment in it, alongside a collaboration on probes, interfaces and test platforms for high-performance computing, advanced packaging, HBM and silicon photonics. Teradyne also holds an investment in Technoprobe, another probe card maker, according to its results release. Advantest sells interface parts too. Its services segment, which includes consumables such as test interface boards for high-performance chips, had first-half sales of ¥75.0 billion, up 53.7%. Our read: the tester makers want the part that touches the chip because it is paid for again with every new design. Our [silicon photonics explainer](https://www.sotkn.com/explained/silicon-photonics-explained/) covers the optical chips that are adding a new kind of test. ## Who are the chip test houses? Test houses are paid to test chips that someone else designed and made. They buy the testers, fill a floor with them and sell the hours. King Yuan Electronics (KYEC) of Taiwan is a test specialist; ASE and Amkor offer test alongside packaging. KYEC’s revenue shows the demand. It reported NT$4.07 billion for September 2026, against NT$3.27 billion a year earlier. Our arithmetic: that is up 24.5%, and January to September revenue of NT$33.48 billion was up 34.1% on the same months of 2025. The bigger change is who pays for the floor. On 21 October 2026 NVIDIA said it is advancing KYEC $1.1 billion to build new US testing facilities and equipment, with high-volume production targeted for April 2027, and that it expects its total testing capacity to double from 2026 to 2027 across the US, Taiwan and Singapore. Our [Wire on NVIDIA’s $1.1 billion test advance](https://www.sotkn.com/wire/nvidia-1-1bn-kyec-amkor-3bn-substrate-capacity-wire/) covers how that prepayment works. Singapore is part of that plan. NVIDIA said expanded testing operations there should begin high-volume production in February 2027, and Amkor lists Singapore among the countries where it runs packaging and test plants, alongside Malaysia, Taiwan and Korea. Our [Singapore markets door](https://www.sotkn.com/markets/singapore/) and [Taiwan markets door](https://www.sotkn.com/markets/taiwan/) follow the two hubs. ![Who tests AI chips: who gets paid in order when an AI chip is tested, from tester makers and probe cards to tester time, test houses and the chip shipping, with tester time as the stuck step](https://storage.ghost.io/c/cd/10/cd10e222-131f-4ba4-b4a9-ca4214e8c12d/content/images/2026/10/who-gets-paid-ai-chip-test.png) Stuck step: tester time. Second Order. ## Who gets paid, and where is the stuck step? Tester makers are paid first, when each system ships. Probe card and interface makers are paid for each new design and again as parts wear. Test houses are paid by the hour once the testers are installed, and now sometimes years in advance. The chip designer is paid last, when a chip that has passed test is sold. The stuck step is tester time. Each AI chip occupies a tester for longer every generation, and adding testers takes months. TrendForce reported that equipment lead times have stretched to six to eight months, from three to six. Advantest says it already has capacity to build more than 5,000 SoC testers a year and aims to reach 10,000 well ahead of its original schedule. Our read: NVIDIA doubling its test capacity from 2026 to 2027 is a large step, but it is smaller than a sevenfold rise in final test time per chip, so either testers check more chips at once or test stays tight. That matches the [reported CoWoS price rises as AI chip tests lengthen](https://www.sotkn.com/wire/tsmc-cowos-price-rise-20-percent-ai-chip-testing-wire/), and it is why the [Semiconductors layer](https://www.sotkn.com/stack/semiconductors/) now treats test as its own bottleneck beside packaging and [CoWoS](https://www.sotkn.com/explained/cowos-explained/). ## What would change the view? - **Testers check more chips at once.** If new testers and probe cards run many more chips in parallel, longer tests per chip would not need proportionally more machines. - **Test moves earlier.** If more faults are caught at wafer sort, before packaging, final test and burn-in could shorten even as chips grow. - **AI chip volumes slow.** Advantest and Teradyne orders follow chip volumes; a pause in AI accelerator builds would hit tester makers first, while test houses keep billing on installed machines. ## What to check next FormFactor reports its third quarter after the US close on 28 October, early on 29 October Singapore time. KYEC publishes October revenue in early November, and Advantest hosts a briefing on its supply chain on 12 November. Our [note on Samsung’s Vietnam test fab](https://www.sotkn.com/markets/korea/korea-samsung-vietnam-test-fab-october-2026/) covers the memory side of the same shortage. ## Common misconceptions - **People assume testing is a quick final check.** Actually each chip is tested several times, and final test for the newest AI chips is estimated to take about seven times as long as it did for Hopper. - **People assume the packaging house does all the testing.** Actually specialist test houses such as KYEC do much of it, and foundries and chip firms run some test themselves. - **People assume more packaging capacity means more chips shipped.** Actually a packaged chip still has to pass test, and tester time is now a separate limit. - **People assume test equipment is a small niche.** Actually SEMI forecasts $15.3 billion of test equipment sales in 2026, more than twice the spend on assembly and packaging tools. ## FAQ **Who tests AI chips?** Four kinds of company. Tester makers such as Advantest and Teradyne build the machines, probe card and interface makers such as FormFactor build the parts that touch each chip, test houses such as KYEC, ASE and Amkor run the test floors, and foundries and chip firms run some test in-house. **What is semiconductor test equipment?** Semiconductor test equipment is the machinery that checks whether each chip works before it ships: automated testers that send signals through the chip, probers and handlers that move wafers and packaged chips into place, and probe cards and sockets that make the electrical contact. **Who makes semiconductor test equipment?** The main makers of automated testers are Advantest of Japan and Teradyne of the US. FormFactor and Technoprobe make probe cards, and Advantest also sells handlers and interface boards. SEMI forecasts $15.3 billion of test equipment sales in 2026. **Why does AI chip testing take longer?** Because each new AI chip packs more silicon, more memory and more connections into one package, and each part must be checked. Nomura estimates, as reported by TrendForce in October 2026, that Blackwell takes about four times as long as Hopper in final test and Rubin about seven times. **What does KYEC do?** King Yuan Electronics (KYEC) is a Taiwanese test house paid to test chips designed and made by others. NVIDIA said on 21 October 2026 that it is advancing KYEC $1.1 billion to build US test capacity, with high-volume production targeted for April 2027. **Is chip testing done in Singapore?** Yes. NVIDIA said expanded testing operations in Singapore should begin high-volume production in February 2027, and Amkor lists Singapore among the countries where it runs packaging and test plants. **Is this a list of stocks to buy or sell?** No. This page explains who does which job and how each gets paid. It does not rank companies or give buy or sell calls. Not investment advice. Do your own research. Related: [advanced packaging](https://www.sotkn.com/explained/who-makes-advanced-packaging/); [CoWoS](https://www.sotkn.com/explained/cowos-explained/); [chiplets](https://www.sotkn.com/explained/chiplet-explained/); [HBM](https://www.sotkn.com/explained/hbm-explained/); [who makes HBM](https://www.sotkn.com/explained/who-makes-hbm/); [who makes AI chips](https://www.sotkn.com/explained/who-makes-ai-chips/). ## Stack doors Layer: [Semiconductors](https://www.sotkn.com/stack/semiconductors/). Also: [TSMC](https://www.sotkn.com/stack/semiconductors/cowos/what-does-tsmc-do/) and [KLA](https://www.sotkn.com/stack/semiconductors/what-does-kla-do/). Markets: [Taiwan](https://www.sotkn.com/markets/taiwan/), [Korea](https://www.sotkn.com/markets/korea/) and [Singapore](https://www.sotkn.com/markets/singapore/). [Get the Wire](https://www.sotkn.com/#/portal/signup) — short daily notes when chips, packaging and test capacity move. Not investment advice. Do your own research. **How we check this** Company figures come from each company’s own results release, presentation, filing or investor relations page, dated in the list below: Advantest, Teradyne, FormFactor, KYEC, NVIDIA and Amkor. The market size comes from SEMI’s equipment forecast. The test-time multiples are a Nomura estimate as reported by TrendForce News, and are labelled as an estimate wherever they appear. The four roles are our grouping, and the payment order is our read of how these contracts work; both are labelled on the page. Sums and percentages marked as our arithmetic are worked from the figures shown. The featured photograph is credited in its caption. This page explains who does which job and how each gets paid. It does not rank companies or give buy or sell calls. Not investment advice. Do your own research. **Last reviewed:** 28 Oct 2026 · **Next review:** after KYEC’s October 2026 revenue (early November) and Advantest’s next results Spot an error? [Tell us](mailto:sean@thekopinotes.com) and we will correct it and note the change here. [Our editorial standards →](https://www.sotkn.com/editorial-standards/) ## References 1. [Advantest — Q2 FY2026 presentation with notes (28 Oct 2026)](https://www.advantest.com/document/en/investors/ir-library/result/JE%5FBIZ%5F261028%5Fnote.pdf?ref=sotkn.com) — SoC test system sales ¥353.3B and memory test system sales ¥53.4B in July–September; CY2026 SoC tester market about $11.5B, memory tester market $2.5–3.0B; SoC tester capacity above 5,000 systems a year, aiming for 10,000; supply constraints expected into CY2027 2. [Advantest — FY2026 second quarter (semi-annual) consolidated financial results (28 Oct 2026)](https://www.advantest.com/document/en/investors/ir-library/result/E%5FFR%5FFY2026%5F2Q.pdf?ref=sotkn.com) — first-half net sales ¥845.2B, up 60.5%; test system segment ¥770.2B, up 61.2%; services segment ¥75.0B including test interface boards; full-year sales forecast raised to ¥1,863.0B from ¥1,714.0B 3. [Teradyne — Reports third quarter 2026 results (27 Oct 2026)](https://investors.teradyne.com/news-events/press-releases/detail/455/teradyne-reports-third-quarter-2026-results?ref=sotkn.com) — revenue $1,306M against $769M a year earlier, of which Semiconductor Test $1,072M; record Memory and Integrated Systems Test revenue; fourth-quarter guide $1,250–1,350M 4. [FormFactor and Teradyne — Strategic collaboration on next-generation semiconductor testing (12 Oct 2026)](https://www.formfactor.com/press-release/formfactor-and-teradyne-announce-strategic-collaboration-to-accelerate-next-generation-semiconductor-testing/?ref=sotkn.com) — Teradyne to make a $300M strategic equity investment in FormFactor; joint work on probes, interfaces and test platforms for HPC, advanced packaging, HBM and silicon photonics 5. [King Yuan Electronics (KYEC) — Monthly revenue, investor relations (accessed 28 Oct 2026)](https://www.kyec.com.tw/en/Ir/Revenue?ref=sotkn.com) — September 2026 revenue NT$4,071,464 thousand against NT$3,271,304 thousand in September 2025; monthly figures January to September 2026 6. [NVIDIA — NVIDIA and supply chain partners expand capacity (GTC Berlin, 21 Oct 2026)](https://nvidianews.nvidia.com/news/nvidia-and-supply-chain-partners-expand-capacity-to-accelerate-ai-infrastructure-buildout?ref=sotkn.com) — NVIDIA expects total semiconductor testing capacity to double from calendar 2026 to 2027 across the US, Taiwan and Singapore; $1.1B capacity reservation advance to KYEC for US test, high volume from April 2027; Singapore high volume from February 2027 7. [Amkor Technology — Form 10-Q for the quarter ended 30 Sep 2026 (filed 27 Oct 2026)](https://www.sec.gov/Archives/edgar/data/1047127/000104712726000052/amkr-20260930.htm?ref=sotkn.com) — net sales $1,990.6M in the quarter; turnkey services from wafer probe to burn-in, system-level and final test; competition from foundries and in-house test; plants include Singapore, Malaysia, Taiwan and Korea 8. [SEMI — Mid-year total semiconductor equipment forecast (14 Jul 2026)](https://www.semi.org/en/semi-press-release/global-semiconductor-equipment-sales-forecast-to-reach-a-record-229-billion-dollars-in-2028-semi-reports?ref=sotkn.com) — semiconductor test equipment sales up 55.3% in 2025 and forecast up 31.0% to $15.3B in 2026, reaching $20.8B in 2028; assembly and packaging equipment $6.7B in 2026 9. [TrendForce News — TSMC reportedly eyes 20% CoWoS price hike (27 Oct 2026)](https://www.trendforce.com/news/2026/10/27/news-tsmc-reportedly-eyes-20-cowos-price-hike-skips-equipment-price-renegotiations-amid-ai-demand-surge/?ref=sotkn.com) — citing Seoul Economic Daily and Nomura: Blackwell final test about four times as long as Hopper, Rubin about seven times; equipment lead times six to eight months, up from three to six S **[Sean](https://www.sotkn.com/author/sean/)** Writes Second Order by TKN — a plain-English map of AI infrastructure and semiconductors for non-specialist investors. Focus: who gets paid, where money sticks, and which step is stuck. Covers AI infrastructure, semiconductors, and second-order stack reads. [Author page →](https://www.sotkn.com/author/sean/) · [Editorial standards →](https://www.sotkn.com/editorial-standards/)