> ## Content Index > Fetch the complete content index at: https://www.sotkn.com/llms.txt > Use this file to discover other available public pages before exploring further. # TSMC, CoWoS Capacity and the Packaging Gate - URL: https://www.sotkn.com/markets/taiwan/tsmc-cowos-capacity/ - Published: 2026-09-14T11:33:14.000Z - Updated: 2026-09-18T16:05:57.000Z - Description: Taiwan owns the AI finish line. Why a CoWoS capacity number means nothing without its variant, and what would show the packaging gate finally loosening. - Author: Sean - Tags: Taiwan, Markets *Taiwan holds the step where an AI accelerator becomes a shippable product. Compute dies are printed there, and — more importantly for supply — they are joined to their memory there. When people say GPUs are short, the binding constraint is frequently a packaging slot in Taiwan rather than a wafer anywhere.* `TAIWAN MARKETS` · `Data as at 19 Sep 2026` · `Next update: after TSMC Q3 2026 results` **Affects:** Semiconductors · Packaging · [Taiwan](https://www.sotkn.com/markets/taiwan/) / [Korea](https://www.sotkn.com/markets/korea/) memory gate **In short:** TSMC runs the dominant share of [CoWoS](https://www.sotkn.com/explained/cowos-explained/) advanced packaging — the finish line for leading AI accelerators. TrendForce put demand about 20% ahead of supply in mid-2026, narrowing toward about 10% by year-end, with reported capacity aiming near 130,000 wafers per month by end-2026 and roughly double that by end-2028\. A capacity number without a variant is nameplate. Packaging is still the stuck step. Education only. Nothing here is a recommendation to buy or sell any security. ### Numbers that matter CoWoS demand vs supply (mid-2026) \~20% short TrendForce, Jun 2026 Still stuck CoWoS demand vs supply (end-2026) \~10% short Narrowing, still open Still stuck Reported CoWoS capacity (end-2026) \~130,000 wpm TrendForce citing local press, 14 Sep 2026 Reported target Reported CoWoS target (end-2028) \~260,000 wpm Roughly double end-2026 level Watch variant mix Who books the slots Top buyers first DigiTimes (Dec 2025): Nvidia >50% of 2026–27 CoWoS Allocation persists Sources: TrendForce (15 Jun 2026; 14 Sep 2026 citing Economic Daily News and Commercial Times); DigiTimes via Taiwan Pulse notes (Dec 2025). Status chips are Second Order's read. Reported targets are not TSMC guidance. ## Why does Taiwan sit at the finish line? Because advanced packaging concentrates there to an unusual degree, and because packaging is the last step that can stop a finished module existing. The chain is short and each link is in a different place. Compute dies come from foundry capacity, largely Taiwanese. Memory stacks come from [Korea](https://www.sotkn.com/markets/korea/). Substrates come from a separate supplier set. Packaging joins them — and if that join is booked, everything upstream queues. Compute die **Who:** Taiwan (TSMC-led) **Paid:** Node capacity and yield; price per wafer Booked on leading nodes Memory stacks (HBM) **Who:** Korea (SK hynix, Samsung) **Paid:** Allocation and qualification Must arrive matched Substrates **Who:** Japan, Taiwan, Korea **Paid:** ABF supply and lead times Watch lead times Advanced packaging (CoWoS) **Who:** Taiwan (TSMC; ASE/SPIL overflow) **Paid:** Whether a finished module exists at all Still the bottleneck Final test **Who:** Taiwan and OSAT network **Paid:** Throughput after the join Follows packaging **What the labels mean:** plain-English status, not a score. Two of the five sit in Taiwan, and one of those two is the finish line. New to the join step? Start with [CoWoS, explained](https://www.sotkn.com/explained/cowos-explained/). For the monthly Taiwan revenue door, see [Taiwan Pulse (Sep 2026)](https://www.sotkn.com/markets/taiwan/taiwan-tsmc-revenue-september-2026/). ![Tall Second Order infographic: where money sticks at Taiwan packaging — compute dies, CoWoS slots (stuck step, red outline), matched HBM. Education only.](https://storage.ghost.io/c/cd/10/cd10e222-131f-4ba4-b4a9-ca4214e8c12d/content/images/2026/09/tsmc-cowos-capacity-infographic.png) Where money sticks at Taiwan's packaging door — CoWoS slots are the stuck step. Education only. ## Why does a CoWoS capacity number mean nothing on its own? Because CoWoS is a family, not a process, and the variants do not substitute freely. As set out in [CoWoS explained](https://www.sotkn.com/explained/cowos-explained/), the three that matter are CoWoS-S on a silicon interposer, CoWoS-R on an organic redistribution layer, and CoWoS-L using local silicon bridges for very large multi-die packages. They differ in density, cost and how easily they scale. ![Horizontal bars comparing CoWoS-S, CoWoS-R and CoWoS-L roles — CoWoS capacity variants do not substitute freely. Second Order Taiwan Markets graphic.](https://storage.ghost.io/c/cd/10/cd10e222-131f-4ba4-b4a9-ca4214e8c12d/content/images/2026/09/tsmc-cowos-capacity-variants.png) CoWoS is a family (S, R, L). A mix shift can raise slots for large packages while leaving the -S queue tight. *"CoWoS capacity doubles next year" can be true while the capacity an in-demand accelerator actually needs barely moves.* Three questions convert a capacity headline into a supply read: 1. **Which variant** is the added capacity in? 2. **Can the accelerators in demand use that variant** without a redesign? 3. **When does it yield**, as opposed to when does construction finish? Without all three, the number is nameplate. A mix shift toward CoWoS-L can raise effective slots for large packages while leaving the -S queue exactly as tight as it was. ## Is CoWoS still the stuck step? Yes. The gap is narrowing, but packaging remains the finish-line gate for leading AI accelerators as at mid-September 2026. TrendForce reported in June 2026 that demand for CoWoS was running about **20% ahead of supply**, narrowing to about **10%** by the end of 2026\. Local press reports summarised by TrendForce on 14 Sep 2026 gave a clearer capacity map: about 130,000 wafers per month by end-2026, with a reported target near 260,000 by end-2028. ![Bar chart of reported CoWoS capacity ~130k wafers/month end-2026 vs ~260k end-2028 target, with demand shortfall narrowing from ~20% to ~10%. Source TrendForce.](https://storage.ghost.io/c/cd/10/cd10e222-131f-4ba4-b4a9-ca4214e8c12d/content/images/2026/09/tsmc-cowos-capacity-capacity.png) Reported CoWoS capacity map and demand shortfall. Sources: TrendForce 15 Jun & 14 Sep 2026\. Not TSMC guidance. Capacity map (reported) End-2026 CoWoS\~130,000 wafers / month End-2028 target\~260,000 wafers / month Mid-2026 shortfall\~20% demand ahead of supply End-2026 shortfall\~10% (narrowing) Two cautions VariantAdded capacity only helps if chips can use it Yield clockConstruction finish ≠ shippable slots Second sourceGate loosens at qualification, not groundbreaking Top-tier bookingLead times for smaller buyers are the honest tell Source: TrendForce, 14 Sep 2026, citing Economic Daily News and Commercial Times; TrendForce demand gap, 15 Jun 2026\. Reported targets, not TSMC guidance. For reading purposes the useful framing is: the packaging gate loosens when the second source qualifies, not when the second site opens. ## What does concentration actually risk? The operational risk is ordinary and continuous: one dominant supplier means one capacity plan, one customer-priority list, and one yield curve setting the pace for the entire AI accelerator market. Customers outside the top tier get whatever is left after the largest buyers book multi-year allocations. The structural risk is that this concentration is geographic as well as corporate. Capacity being added elsewhere — in the US, Japan and through OSAT partners — reduces it slowly, and only for the variants that transfer easily. Advanced packaging is not a process that relocates quickly, because the constraint is tooling, trained operators and yield learning rather than floor space. ## How does this interact with the memory gate? They have to arrive matched, which is the part most commentary misses. A packaging slot with no memory stacks is an idle slot. Memory stacks with no packaging slot are inventory. Either failure produces the same visible outcome — finished accelerators are late — and the two are frequently confused for one another. [HBM4 tightens this coupling further](https://www.sotkn.com/explained/hbm-explained/), because a wider memory interface pushes more difficulty into the attach step itself. The next generation makes Taiwan and Korea more dependent on each other's timing, not less. Read the Korea door: [SK Hynix and the HBM allocation cycle](https://www.sotkn.com/markets/korea/sk-hynix-hbm-allocation/) and [Korea Pulse](https://www.sotkn.com/markets/korea/korea-hbm-memory-september-2026/). This is why the two country lanes are read together but not merged. The question is always *which* gate is binding this quarter, and the answer changes. ## How do international readers get exposure? Taiwanese foundry and packaging names are accessible to many international brokers through ADRs as well as local listings, with the usual caveats about share class, liquidity and tax treatment. Exposure also arrives through the substrate and equipment suppliers that feed the packaging step. If you use Interactive Brokers, this soft referral link opens an account path: [Interactive Brokers referral](https://www.interactivebrokers.com/referral/jianxiong368?ref=sotkn.com). That is access language, not a recommendation. Second Order does not publish buy lists. ## What would change this view? The tight read on the packaging gate weakens if: - Added capacity is confirmed in the variant that in-demand accelerators actually use - A second supplier qualifies on a leading accelerator programme, not merely announces capability - Lead times shorten for buyers outside the top tier — the most honest single indicator - Substrate and memory supply start arriving matched rather than staggered - Accelerator designs shift toward fewer packaging slots per unit of compute - Memory, rather than packaging, becomes the louder gate again It stays tight while allocation persists for non-top-tier buyers and variant mix absorbs the headline capacity adds. ### Practical takeaways - Taiwan owns the finish line, not merely a large share of wafers - A CoWoS capacity number without a variant is nameplate - The gate loosens at qualification, not at groundbreaking - Memory and packaging must arrive matched; either one late produces the same symptom - Lead times for smaller buyers are the most honest tightness signal ## FAQ **Why is Taiwan so important to AI chips?** It holds both leading-edge foundry capacity and the dominant share of advanced packaging. Packaging is the step that decides whether a finished accelerator module exists, which makes it the finish line for AI GPU supply. **What is CoWoS capacity?** The throughput of TSMC's advanced packaging family that joins compute dies to high-bandwidth memory. It is usually the binding constraint on leading AI accelerator supply. **Does more CoWoS capacity mean more GPUs?** Only if the added capacity is in the variant the in-demand accelerators use, and only once it yields. Capacity announcements and shippable supply run on different clocks. **How does the Taiwan packaging gate relate to Korean memory?** They are neighbouring gates that must arrive matched. A slot without stacks is idle; stacks without a slot are inventory. Either produces late accelerators. **Is the CoWoS shortage over?** Not yet. TrendForce estimated demand was about 20% ahead of supply in mid-2026, narrowing to about 10% by year-end, with reported capacity aiming to roughly double by the end of 2028. **What would show the packaging bottleneck easing?** Shorter lead times for buyers outside the top tier, and a second supplier qualifying on a leading programme rather than announcing capability. ### Keep reading on the map - **Explained:** [CoWoS, explained](https://www.sotkn.com/explained/cowos-explained/) · [HBM, explained](https://www.sotkn.com/explained/hbm-explained/) - **Markets:** [Taiwan](https://www.sotkn.com/markets/taiwan/) · [Taiwan Pulse](https://www.sotkn.com/markets/taiwan/taiwan-tsmc-revenue-september-2026/) · [Korea](https://www.sotkn.com/markets/korea/) - **Stack doors:** [Semiconductors](https://www.sotkn.com/semiconductors/) · [Hyperscalers](https://www.sotkn.com/hyperscalers/) · [Neoclouds](https://www.sotkn.com/neoclouds/) **Members' Analysis:** If CoWoS capacity roughly doubles by 2028, where does the stuck step move, and who gets paid there? The free part: memory and power are the two candidates. **[Read the Analysis →](https://www.sotkn.com/analysis/)** **Get the Wire.** One short email, at most twice a week, on what changed in the AI chip map. [Subscribe free →](https://www.sotkn.com/#/portal/signup) --- **How we made this** Upgraded from the Sep 2026 packaging-gate Markets piece to the locked Taiwan Pulse presentation (in-short speakable box, signal/chain stacks, FAQPage schema, image pack). Dated capacity figures refreshed from TrendForce (Jun and Sep 2026). Thesis unchanged. **Sources** - TrendForce CoWoS demand/supply notes, 15 Jun 2026 and 14 Sep 2026 (citing Economic Daily News / Commercial Times) - TSMC public materials on CoWoS family; Second Order [CoWoS explained](https://www.sotkn.com/explained/cowos-explained/) - DigiTimes reporting on Nvidia CoWoS booking share (Dec 2025), as cited in Taiwan Pulse - Cross-links to Korea Pulse / HBM explained for the matched-arrival rule Disclaimer: Education only. Not investment advice. Figures are as reported by named sources on the dates shown; reported capacity targets are not company guidance. Second Order may update this door when Q3 results or new capacity disclosures land.