> ## Content Index > Fetch the complete content index at: https://www.sotkn.com/llms.txt > Use this file to discover other available public pages before exploring further. # What Does TSMC Do? The CoWoS Packaging Model - URL: https://www.sotkn.com/stack/semiconductors/cowos/what-does-tsmc-do/ - Published: 2026-09-29T04:52:29.000Z - Updated: 2026-09-29T04:52:29.000Z - Description: TSMC prints compute dies and joins them to HBM on CoWoS — it gets paid when finished modules ship, and packaging slots are the stuck step. - Author: Sean - Tags: #layer-cowos *TSMC prints leading-edge compute dies and joins them to HBM on CoWoS — it gets paid when a finished module ships, and packaging slots, not wafer starts, are the stuck step.* `COWOS` · `Data as at 29 Sep 2026` · `Next update: after Q3 2026 results` **Affects:** Semiconductors · CoWoS · Taiwan It is the foundry that prints most leading AI accelerators, and the packager that joins those dies to [HBM](https://www.sotkn.com/explained/hbm-explained/) on [CoWoS](https://www.sotkn.com/explained/cowos-explained/). That is a different job from [SK hynix](https://www.sotkn.com/stack/semiconductors/hbm/what-does-sk-hynix-do/), which builds the stacks. For the country door, see [Taiwan TSMC revenue](https://www.sotkn.com/markets/taiwan/taiwan-tsmc-revenue-september-2026/). For the dated packaging path, see the [Wire on CoWoS-L through 2028](https://www.sotkn.com/wire/cowos-l-mainstream-through-2028-wire/). **In short:** TSMC makes other companies’ chips, then packages the AI ones. Q2 2026 revenue was NT$1,270.38bn (US$40.20bn), with a 67.7% gross margin and 60.3% operating margin. HPC was 66% of sales. The model works if CoWoS slots keep matching the wafers — Chairman C.C. Wei said on 16 July 2026 that packaging was “so tight that now it limits my customers’ growth.” *Education only. Figures are from company filings and company releases dated as shown.* ## Numbers that matter Q2 2026 revenue NT$1,270.38bn US$40.20bn · +12.0% QoQ · +36.0% YoY · quarter ended 30 Jun 2026 **Record** Gross / operating margin 67.7% · 60.3% Net income NT$706.56bn · +77.4% YoY **Pricing power** Packaging vs wafers Slots bind C.C. Wei, Q2 call, 16 Jul 2026 — packaging “limits my customers’ growth” **Stuck** HPC share of sales 66% +20% QoQ · 7nm-and-below 77% of wafer revenue **AI mix** FY2026 cash capex US$60–64bn \~10–20% packaging / testing / mask / others · Q2 spent US$15.70bn **Gate funded** August 2026 sales NT$514.81bn +53.3% YoY · +10.1% MoM · Jan–Aug NT$3,386.87bn **Demand loud** Sources: TSMC Q2 2026 results, 16 Jul 2026; TSMC monthly revenue, 10 Sep 2026\. Status chips are Second Order's read. **Contents:** [What does TSMC actually do?](#what-it-does) · [How does it make money?](#how-it-earns) · [What limits it?](#what-limits) · [Who else does this?](#who-else) · [What would change this view](#what-would-change) · [Practical takeaways](#practical-takeaways) · [FAQ](#faq) --- ## What does TSMC actually do? Three steps, in order. CoWoS · TSMC**Print. Join. Ship.**01 ### Print Leading-edge wafers for other companies’ chips. 7nm-and-below was 77% of wafer revenue in Q2. 02 ### Join CoWoS attaches the die to HBM. This is the stuck step — a wafer is not a module. 03 ### Ship The finished accelerator leaves only when the slot yields. Buyers invoice after that. Source: Second Order reading of TSMC Q2 2026\. Educational only. Not a buy list. **1\. It prints other companies’ chips.** TSMC is a pure-play foundry: it does not sell its own GPU brand. Designers send the layout; TSMC prints the die. In Q2 2026, 2-nanometre was 3% of wafer revenue, 3nm 30%, 5nm 33%, and 7nm 11%. Advanced technology, defined as 7nm and below, was 77% of wafer revenue (16 Jul 2026). HPC, mostly AI and data-centre silicon, was 66% of total revenue and rose 20% quarter-on-quarter. See [foundry and advanced packaging](https://www.sotkn.com/explained/foundry-advanced-packaging-explained/). **2\. It joins the die to memory.** An AI accelerator is not finished on the wafer. It still needs [CoWoS](https://www.sotkn.com/explained/cowos-explained/) — chip-on-wafer-on-substrate — to sit the compute die millimetres from HBM stacks. TSMC’s public CoWoS page describes three variants: CoWoS-S (silicon interposer, up to about 3.3× reticle), CoWoS-R (organic RDL), and CoWoS-L (RDL plus local silicon interconnects for very large multi-die packages). CoWoS has been in production since 2012\. The AI cash bind is not “any CoWoS line.” It is the scarce style the newest accelerators need — today, usually CoWoS-L. Our [Wire](https://www.sotkn.com/wire/cowos-l-mainstream-through-2028-wire/) keeps that path as the packaging default through 2028. **3\. It ships a module, not a wafer story.** TSMC gets paid when the customer takes the part. A front-end start that cannot clear a packaging slot does not become a GPU in a [neocloud](https://www.sotkn.com/stack/neoclouds/what-does-coreweave-do/) or [hyperscaler](https://www.sotkn.com/stack/hyperscalers/what-does-oracle-do/) rack. That is why Chairman C.C. Wei, answering a question about competing packaging routes on the 16 July 2026 call, said packaging capacity “is so tight that now it limits my customers’ growth,” and that extra routes would help TSMC’s front-end wafer business — “which is a majority part of TSMC’s business.” | Step | What it means | Where the risk sits | | ----- | ------------------------------------------------ | ------------------------------------------------------------- | | Print | Leading-edge wafers for other companies’ designs | Node mix, yield, overseas-fab dilution | | Join | CoWoS-class attach of die + HBM | Slots, variant (S / R / L), tool qualification | | Ship | Finished module leaves the line | A wafer that cannot attach does not invoice as an accelerator | --- ## How does TSMC make money? It gets paid for silicon that ships. On the AI layer, that is wafers *and* the package. Three things decide the print: - **Mix** — HPC and leading-edge nodes earn more than older smartphone or mature parts on the same tool set - **Utilisation** — a full leading-edge line plus a scarce CoWoS slot is what a 67.7% gross margin looks like - **The join** — a die that cannot attach does not become an AI module, however good the wafer yield looks On 16 July 2026 TSMC printed NT$1,270.38 billion of revenue and NT$766.60 billion of operating income for the quarter ended 30 June 2026\. Gross profit was NT$860.31 billion. Net income attributable to shareholders was NT$706.56 billion. In US dollars, revenue was $40.20 billion, up 12.0% sequentially and 33.7% year-on-year, at the high end of guidance. **Our arithmetic.** Gross margin: 860.31 ÷ 1,270.38 = **67.7%**. Operating margin: 766.60 ÷ 1,270.38 = **60.3%**. Net income grew 77.4% year-on-year while revenue grew 36.0% — profit outrunning sales is the pricing-power tape, not a volume slogan. Q3 guidance is US$44.6–45.8 billion of revenue, 65–67% gross margin, 56–58% operating margin. The midpoint gross-margin step-down is the 2nm ramp: management said that ramp dilutes gross margin by about 3 to 4 percentage points in the second half, partly offset by leading-edge demand and cost improvement. | | Q2 2026 | Share / note | | ---------------- | -------------------------- | -------------------------------- | | Net revenue | NT$1,270.38bn / US$40.20bn | +12.0% QoQ | | Gross profit | NT$860.31bn | **67.7%** | | Operating income | NT$766.60bn | **60.3%** | | Q2 cash capex | US$15.70bn | **39%** of quarterly US$ revenue | **Our check:** 15.70 ÷ 40.20 = 39.1%, which we round to 39%. TSMC spent about two-fifths of a record quarter’s dollar sales putting more tools in the ground. Full-year 2026 cash capex was raised to US$60–64 billion. About 70–80% of that budget is advanced process, about 10% specialty, and about 10–20% “advanced packaging, testing, mask making and others.” That last bucket is not a pure CoWoS line item. At the midpoint of the cash guide (US$62bn), 10–20% is **US$6.2–12.4bn** for the whole packaging-and-other bucket — our arithmetic, not a CoWoS wafers-per-month figure. August sales kept the same story on a monthly tape. TSMC reported NT$514,806 million for August 2026, up 53.3% year-on-year. January–August was NT$3,386,870 million, up 39.3%. **Our check versus July:** 514.806 ÷ 467.580 = 1.101 → **+10.1%** month-on-month. Demand is not waiting for packaging to catch up. See the [August revenue Pulse](https://www.sotkn.com/markets/taiwan/taiwan-tsmc-revenue-september-2026/). Who gets paid: TSMC, on scarce wafers and scarce CoWoS slots. Money sticks at the join. A board cheque for tools is not yet a yielded slot — see the [capex-split Pulse](https://www.sotkn.com/markets/taiwan/taiwan-tsmc-capex-split-september-2026/). --- ## What limits it? Packaging first. Variant second. HBM and power as neighbours. **1\. CoWoS slots, not wafer starts.** Wei’s 16 July sentence is the primary IR print: packaging tightness limits customer growth. TSMC does not publish a single official CoWoS wafers-per-month figure in the earnings release. Dated trade research (TrendForce, 15 Jun 2026) put TSMC around 120,000–140,000 wafers/month in 2026 with OSAT partners adding more, and a supply-demand gap narrowing from about 20% to about 10% by year-end — research estimates, not filings. Built is not yielded. Yielded is not allocated to second-tier buyers. Watch lead times. See [TSMC, CoWoS capacity and the packaging gate](https://www.sotkn.com/markets/taiwan/tsmc-cowos-capacity/). **2\. The family is not one queue.** CoWoS-S, CoWoS-R, and CoWoS-L are different machines in commercial fact. A “more CoWoS” headline that does not name the variant can add the wrong slots. TrendForce (18 Sep 2026) keeps CoWoS-L as the mainstream AI packaging path through 2028\. Intel’s EMIB-T is a 2027 option on a yield climb, not a 2026 escape valve — that is the [Wire](https://www.sotkn.com/wire/cowos-l-mainstream-through-2028-wire/) read. On the same July call, Wei said the majority path is still CoWoS, and that a glass-substrate alternative needs about another year to mature for customer production. **3\. A cheque is not a slot.** The 24 September 2026 Form 6-K split the August board check: US$16,035 million of advanced-technology machinery, US$4,791 million of machinery for advanced packaging, mature and/or specialty capacity, and US$8,616 million of real estate and capitalized leased assets. **Our check:** 16.035 + 4.791 + 8.616 = **29.442**. The packaging line is 4.791 ÷ 29.442 = **16.3%** of that check — bundled with mature and specialty tools. It funds the gate. It does not print CoWoS-L wafers per month. First-half cash capex was US$26.80 billion. Baipu (21 Sep) is a validation hub aimed at Q4 2029, not this year’s volume line. See [Baipu](https://www.sotkn.com/markets/taiwan/taiwan-baipu-cowos-validation-september-2026/). **4\. HBM can re-bind after the die is printed.** CoWoS exists to attach stacks. If the cube is late, the reserved slot slips. If the slot is late, the cube sits. Either clock can set the ship date. That neighbour is Korea, not Taiwan — [What Does SK hynix Do?](https://www.sotkn.com/stack/semiconductors/hbm/what-does-sk-hynix-do/). The honest uncertainty is conversion of authorised tools into the *right* variant at yield. A company can print NT$514.81bn of August sales and still ration CoWoS-L. It can raise a US$60–64bn cash budget and still have packaging limit customer growth. Those are different clocks. We are not going to pretend a 6-K line item settles both. --- ## Who else does this? Roles, not a league table. | Company | What it does | What makes it different | | --------------------- | ----------------------------------------- | ------------------------------------------------------------------------------------------------------------------ | | **TSMC** | Leading-edge foundry + branded CoWoS | Prints the die and owns the attach gate; 67.7% gross margin; packaging still limiting growth (16 Jul 2026) | | **ASE (incl. SPIL)** | OSAT overflow beside TSMC | Adds CoWoS-class packaging; CapEx is a capacity-add clock, not a cleared queue | | **Intel** | EMIB-T as an alternative join | 2027 customer path on substrate yield, not 2026 CoWoS-L volume | | **Samsung** | Memory + foundry + own advanced packaging | Only large name that can try logic, HBM, and attach under one roof | | **SK hynix / Micron** | HBM stacks that go into the package | Neighbours, not substitutes. See [SK hynix](https://www.sotkn.com/stack/semiconductors/hbm/what-does-sk-hynix-do/) | The question that separates them is who holds the scarce attach slot the leading accelerator actually uses — and whether the HBM cube is ready the same day. --- ## What would change this view? The read on the model weakens if: - TSMC’s next earnings call says packaging is no longer limiting customer growth — in those words, or equivalent - A dated CoWoS-L (not “CoWoS”) wafers-per-month print shows the gap closing for buyers outside the top of the book - A second packager qualifies volume on a leading AI accelerator — qualification, not a capability slide - Gross margin falls below the guided range for reasons other than the disclosed 2nm and overseas-fab ramps - HBM, not packaging, becomes the louder gate on GPU ship dates — the stuck step would then sit in [Korea](https://www.sotkn.com/markets/korea/) - Power for finished racks, not the Taiwan join, becomes the louder bind — then re-weight to [speed-to-power](https://www.sotkn.com/explained/speed-to-power-explained-for-investors/) It stays intact while HPC stays the majority of sales, packaging language stays tight, CoWoS-L remains the mainstream large-package path, and monthly sales keep climbing on a stuck join. --- ## Practical takeaways - TSMC’s AI model on this layer is **Print → Join → Ship**: leading-edge wafers, CoWoS attach, then a finished module - Q2 2026: NT$1,270.38bn revenue (US$40.20bn), 67.7% gross margin, 60.3% operating margin, HPC 66% of sales - The stuck step is **CoWoS slots** — Wei, 16 Jul 2026 — not “did TSMC start enough wafers” - FY2026 cash capex US$60–64bn; only 10–20% is the packaging/testing/mask/other bucket, and the 24 Sep 6-K packaging line is bundled with mature/specialty - Next hard read: TSMC Q3 2026 results (15 Oct) — cash capex versus the band, and any packaging language that names a variant --- ## FAQ **What does TSMC do?** TSMC is a pure-play foundry and advanced packager. It prints leading-edge logic wafers for other companies’ chips and, for AI accelerators, joins the compute die to HBM on CoWoS so a finished module can ship. **What does TSMC do in simple terms?** It makes the AI chip and then glues it to the tall memory stacks. The glue step is what runs short. **Is TSMC profitable?** Yes, on a reported operating basis. It posted NT$766.60 billion of operating income on NT$1,270.38 billion of revenue in the quarter ended 30 June 2026 — a 60.3% operating margin and a 67.7% gross margin (16 Jul 2026). Net income was NT$706.56 billion. **How is TSMC different from SK hynix?** SK hynix makes the HBM stacks. TSMC prints the compute die and joins those stacks on CoWoS. From HBM4, SK hynix also buys a TSMC logic base die. They are neighbours on the same module, not substitutes. See [What Does SK hynix Do?](https://www.sotkn.com/stack/semiconductors/hbm/what-does-sk-hynix-do/). **What is CoWoS?** Chip-on-wafer-on-substrate — TSMC’s packaging family that places a compute die and HBM on a shared base, then onto a substrate. Variants are CoWoS-S, CoWoS-R, and CoWoS-L. See [CoWoS, explained](https://www.sotkn.com/explained/cowos-explained/). **Should I buy TSMC shares?** We do not make buy or sell calls, and nothing here is a recommendation. What we can tell you is what the company does, how it gets paid, and which figures would change the picture. The decision is yours. --- ## Keep reading on the map - **The layer:** [CoWoS](https://www.sotkn.com/stack/semiconductors/cowos/) — inside [semiconductors](https://www.sotkn.com/stack/semiconductors/) - **The term:** [CoWoS, explained](https://www.sotkn.com/explained/cowos-explained/) · [foundry and advanced packaging](https://www.sotkn.com/explained/foundry-advanced-packaging-explained/) - **The Wire:** [CoWoS-L through 2028](https://www.sotkn.com/wire/cowos-l-mainstream-through-2028-wire/) - **Where it happens:** [Taiwan](https://www.sotkn.com/markets/taiwan/) — [August revenue](https://www.sotkn.com/markets/taiwan/taiwan-tsmc-revenue-september-2026/) · [August capex split](https://www.sotkn.com/markets/taiwan/taiwan-tsmc-capex-split-september-2026/) - **The neighbour stack:** [What Does SK hynix Do?](https://www.sotkn.com/stack/semiconductors/hbm/what-does-sk-hynix-do/) ## Members' Analysis: if CoWoS-L stays the path through 2028, who captures the next dollar? The free part: a 67.7% gross margin next to a chairman saying packaging limits customer growth is what a scarce attach step looks like in a dated print. The members cuts are live: [Where does the stuck step move?](https://www.sotkn.com/analysis/where-does-the-stuck-step-move/) · [If CoWoS-L stays mainstream through 2028](https://www.sotkn.com/analysis/cowos-l-through-2028-capacity-or-validation/). This page stays the free Stack read of the TSMC CoWoS model. ## Sean Writes Second Order by TKN — a plain-English map of AI infrastructure and semiconductors for non-specialist investors. Focus: who gets paid, where money sticks, and which step is stuck. Not investment advice. [Author page →](https://www.sotkn.com/author/sean/) · [Editorial standards →](https://www.sotkn.com/editorial-standards/) ## How we check this Figures come from company filings and company releases, each dated below. Capacity from the earnings call is the company’s spoken print, not our estimate. Wafers-per-month tables from research houses are labelled as estimates, not filings. Where we work something out ourselves, the arithmetic is shown in full. **Last reviewed:** 29 Sep 2026 · **Next review:** after Q3 2026 results (15 Oct). Spot an error? Tell us and we will correct it. [Editorial standards →](https://www.sotkn.com/editorial-standards/) ## Sources 1. TSMC, [Q2 2026 earnings release](https://www.sec.gov/Archives/edgar/data/1046179/000104617926000451/a2q26e%5Fwithguidancexfinal.htm?ref=sotkn.com) (SEC), 16 Jul 2026 — revenue, gross/operating/net income, margins, node mix, Q3 guidance 2. TSMC Q2 2026 earnings call transcript, 16 Jul 2026, via [TSMC quarterly results](https://investor.tsmc.com/english/quarterly-results/2026/q2?ref=sotkn.com) — HPC 66%, capex US$60–64bn and mix, Wei on packaging tightness, 13 Taiwan fabs, Arizona +US$100bn, CoWoS still majority / glass \~1 year 3. TSMC Q2 2026 management / presentation materials, 16 Jul 2026 — Q2 cash capex US$15.70bn; YTD US$26.80bn; wafer shipments 4,336k 12-inch equivalent 4. TSMC, [2026 monthly revenue](https://investor.tsmc.com/english/monthly-revenue/2026?ref=sotkn.com), August print 10 Sep 2026 — NT$514,806m, +53.3% YoY; Jan–Aug NT$3,386,870m, +39.3% 5. TSMC, [Form 6-K](https://www.sec.gov/Archives/edgar/data/1046179/000104617926000660/tsm-monthend6kx20260924.htm?ref=sotkn.com), 24 Sep 2026 — August board split US$16.035bn / US$4.791bn / US$8.616bn 6. TSMC, [CoWoS technology page](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm?ref=sotkn.com) — S / R / L; production since 2012 7. TrendForce, 15 Jun 2026 — CoWoS WPM and S/D gap (research estimate, not a filing) 8. Second Order, [CoWoS-L through 2028](https://www.sotkn.com/wire/cowos-l-mainstream-through-2028-wire/) — TrendForce 18 Sep 2026 path 9. Second Order, [August capex split Pulse](https://www.sotkn.com/markets/taiwan/taiwan-tsmc-capex-split-september-2026/) — 6-K arithmetic All external links `rel="nofollow noopener"`.