> ## Content Index > Fetch the complete content index at: https://www.sotkn.com/llms.txt > Use this file to discover other available public pages before exploring further. # Advanced packaging hits $28 billion in 2026 as TSMC's CoWoS queue forced Nvidia to finance its own backup - URL: https://www.sotkn.com/wire/advanced-packaging-28-billion-cowos-tsmc-nvidia-spil-wire/ - Published: 2026-11-08T23:58:19.000Z - Updated: 2026-11-09T00:03:36.000Z - Description: Advanced-packaging capex hit $28B in 2026 — first year revenue overtakes traditional packaging. TSMC dominates CoWoS. Nvidia is financing billions at SPIL to escape the queue. Memory makers now pay TSMC for every HBM base die. - Author: Sean - Tags: #desk-wire `WIRE` · `SEMICONDUCTORS` · `TAIWAN` · Data as at 9 Nov 2026 **Yole Group expects 2026 advanced-packaging capex near $28 billion** — the first year packaging revenue overtakes traditional packaging. TSMC dominates CoWoS, the technology that bonds GPUs and HBM stacks into one unit. Nvidia is reportedly financing billions at SPIL (an ASE subsidiary) to build CoWoS capacity outside the queue. Memory makers now pay TSMC for the base dies inside their own HBM stacks. The bottleneck moved from the fab to the packager. ## What happened THE NUMBER **$28 billion** Advanced-packaging capex in 2026 — the first year packaging revenue overtakes traditional packaging. Yole Group estimate via Reuters, 6 Nov 2026. THE SQUEEZE **TSMC CoWoS is the queue** TSMC dominates chip-on-wafer-on-substrate, the advanced-packaging technology linking AI processors and HBM memory; Nvidia, AMD and Broadcom rely on it, but capacity is tight. THE ESCAPE **Nvidia → SPIL** Nvidia is reportedly providing billions in financing to expand CoWoS capacity at SPIL (a unit of ASE Technology); amount, terms and timing undisclosed; neither Nvidia nor ASE commented. Reuters, 6 Nov 2026. THE REQUEST **TSMC + 3D DRAM** TSMC began drafting plans to produce 3D DRAM at Nvidia’s request — The Information, 6 Nov 2026, two people familiar; nothing committed; TSMC does not comment on market rumours. ## Why cash cares A chip is designed. It is fabricated. And then it is packaged — bonded to memory, mounted on a substrate, and sealed for shipping. For decades, that last step was logistics. In 2026 it became the constraint. Yole Group expects advanced-packaging capital spending to near $28 billion in 2026 — and for the first time, advanced-packaging revenue to overtake the revenue earned by traditional packaging. Reuters reported this on 6 November after interviews with more than a dozen industry executives and analysts. At the centre of the shortage is TSMC’s CoWoS technology. Chip-on-wafer-on-substrate links a processor, such as an Nvidia H100 or Blackwell GPU, to its HBM memory stack using a silicon interposer, allowing data to flow between them at speeds a standard circuit board cannot match. Nvidia, AMD and Broadcom rely on it. Cloud companies designing their own AI chips rely on it. The queue is long. ## What is CoWoS — and why it became the stuck step CoWoS bonds the processor die and the HBM dies onto a shared substrate, then encapsulates the assembly. What matters is the interposer — a layer of silicon with wiring so short and dense that the bandwidth between processor and memory runs at terabits per second. Without that link, an AI chip cannot feed its compute fast enough to stay useful. TSMC built the interposer technology and owns the most advanced CoWoS lines. Building more CoWoS requires expensive bonding equipment, clean rooms rated for the process, and engineers who know the yields. Equipment lead times run to years. Capacity cannot sprint when demand arrives. The result is what Lisa Su, AMD’s chief executive, described to Reuters in October: “We do need more capacity overall.” AMD has invested more than $10 billion across Taiwan’s semiconductor industry, including packaging partnerships with ASE, SPIL and Powertech — roughly 36% of Yole’s $28 billion figure on our arithmetic. Powertech is building a $400 million advanced-packaging joint venture with Broadcom in Singapore, about 1.4% of the Yole capex figure on our arithmetic. Neither project is CoWoS — both are exploring panel-level packaging, which uses rectangular panels instead of round wafers and wastes less material on larger chips. TSMC is developing its own panel-level technology, called CoPoS, though CoWoS remains its primary AI-packaging product. ![Advanced packaging in 2026: $28B capex, first year revenue overtakes traditional, Nvidia-SPIL CoWoS financing, AMD $10B+ Taiwan investment, SK hynix DRAM/HBM sold out through 2029](https://storage.ghost.io/c/cd/10/cd10e222-131f-4ba4-b4a9-ca4214e8c12d/content/images/2026/11/wire_figure_advanced_packaging.png) **Figure: Advanced packaging in 2026 — the new bottleneck in numbers.** Advanced-packaging capex \~$28B; packaging revenue overtakes traditional for first time; Nvidia → SPIL CoWoS financing (undisclosed); AMD Taiwan investment >$10B; Powertech-Broadcom Singapore JV $400M; SK hynix DRAM/HBM sold out through 2029\. Our arithmetic: AMD $10B ÷ Yole $28B ≈ 36%; Powertech $400M ÷ Yole $28B ≈ 1.4%. Reuters / Yole Group, 6 Nov 2026; AMD investor relations, 3 Nov 2026; SK hynix Q3 call, 28 Oct 2026. ## The second-order read: who gets paid, who pays, who waits **Who gets paid.** TSMC collects twice. It earns logic foundry revenue when Samsung, SK hynix and Micron contract it to make the base dies for Nvidia’s next-generation custom HBM — called NVHBM — on its 3nm process. And it earns CoWoS packaging revenue when those stacks go through its advanced-packaging lines. The Seoul Economic Daily reported in October 2026 that Nvidia asked all three memory makers to build NVHBM base dies on TSMC’s 3nm process, and that Samsung’s Device Solutions division accepted after an internal review. SK hynix had already been using TSMC’s 12nm process for earlier HBM4 base dies and is now prioritising 3nm for future custom versions; Micron has confirmed plans to outsource its HBM4E and NVHBM base dies to TSMC, expecting volume production by 2027. ASE and SPIL collect next. ASE’s packaging arm turns substrate, bonding and test into a margin line; SPIL is now reportedly receiving financing from Nvidia itself to expand CoWoS-equivalent capacity. Applied Materials, Tokyo Electron and Advantest are downstream of that capex — equipment orders precede the capacity they create. Applied Materials reports on Friday 13 November. **Who pays.** The memory makers face a double payment: TSMC’s 3nm logic price for the base die, and TSMC’s CoWoS price to assemble the stack. That is a new cost structure for HBM. Samsung, SK hynix and Micron have been integrating base die and core die manufacturing on their own processes for years; outsourcing the base die to TSMC’s logic process raises their bill in exchange for the yield consistency that Nvidia’s standardisation requires. Industry estimates put TSMC’s 3nm yield above 90%, while Samsung’s equivalent foundry process is estimated around 60% — estimates, not independently validated production data, and not directly comparable across different nodes. **Who waits.** TSMC’s existing customers — Nvidia, AMD, Broadcom — wait longer for every byte of CoWoS capacity that memory base die work consumes. TSMC US-listed shares rose 6.33% to $375.44 on 6 November as markets weighed whether the memory work adds to or competes with its AI chip packaging line. The memory supply itself is locked. Samsung said at its Q3 earnings call that 2027 HBM is fully sold with pricing negotiated at target levels. SK hynix reported that DRAM and HBM output is effectively sold out through 2029, with long-term agreements covering more than 50% of 2027 and 2028 capacity. Micron expects the shortage to last until 2028. **AMD shows the demand.** AMD reported record Q3 2026 revenue of $13.4 billion, up 45% year on year. Data Center revenue was $8.5 billion, up 97%, which is 63.4% of the total — our arithmetic on AMD’s reported segment figures. Lisa Su guided Data Center revenue to grow roughly 50% sequentially in Q4\. Applied to the $17 billion Q4 guidance midpoint, that implies Data Center revenue of approximately $12.8 billion, or roughly 75% of the total — our arithmetic. Every AI chip AMD ships needs CoWoS. AMD needs more packaging capacity, and so does everyone else in the queue. ## Two cautions The Nvidia-SPIL CoWoS financing figure is “billions of dollars” from a single industry executive who spoke on condition of anonymity to Reuters. Neither Nvidia nor ASE confirmed the amount, terms or timing. The scale of that commitment is unverified beyond the direction of travel. TSMC’s 3D DRAM review is at the drafting stage. No factory location, investment budget, wafer target, product specification or production date has been set. TSMC does not comment on market rumours. The gap between a planning review and production capacity in memory is measured in years; TSMC’s 3nm process faces competing demand from AI accelerators and smartphones, which could constrain the NVHBM base die allocation regardless of the 3D DRAM question. The Seoul Economic Daily noted in October that Samsung is validating its own 2nm foundry as a hedge if TSMC capacity runs short. ## What would change the view If TSMC were to announce a disclosed CoWoS capacity commitment with named customers and a production ramp date, the packaging bottleneck moves from qualitative to quantifiable. If AMD, Nvidia or a memory maker were to disclose the NVHBM base die arrangement with volume and pricing, the double-payment cost structure for HBM becomes reportable margin data. If the SPIL financing were disclosed — amount, term, ownership — it would reveal how much of the packaging capacity Nvidia is effectively pre-funding. If TSMC’s 3D DRAM review progresses to a site selection or fab acquisition, the memory supply map for 2028 onwards changes. ## What to watch - **TSMC October monthly revenue, Tuesday 10 Nov 2026, 13:30 Taipei:** First readout against Q4 guidance of $52.3–54.3 billion. Progress signals whether CoWoS-driven demand is on track. - **Applied Materials full-year results, Friday 13 Nov 2026:** Equipment demand for advanced packaging and CoWoS-compatible tools is a leading indicator of capacity coming online in 2027. - **CoreWeave Q3 earnings, Wednesday 11 Nov 2026:** Backlog and GPU package delivery status; CoreWeave depends on CoWoS for every chip it rents. - **NVHBM volume production timing:** When Samsung, SK hynix or Micron confirms TSMC 3nm base die volume enters NVHBM stacks and at what pricing. - **SPIL financing disclosure:** Whether Nvidia or ASE ever put a disclosed number and terms on the CoWoS commitment. *Read: [Semiconductors — Buyers Fund the Factory](https://www.sotkn.com/stack/semiconductors/) on the SOTKN stack* --- **Get the Wire.** A free brief every day, here and in your inbox. **[Subscribe free →](https://www.sotkn.com/#/portal/signup)** If this Wire saved you a search, tip Second Order → [sotkn.com/support](https://www.sotkn.com/#/portal/support) Not investment advice. Do your own research. The 63.4% and \~75% AMD Data Center revenue shares, the 36% and 1.4% capex comparisons, and the TSMC TSM share move are our arithmetic on reported figures. ## References 1. [Reuters (Wen-Yee Lee), “AI boom turns chip packaging into the next battleground for semiconductors,” 6 Nov 2026](https://money.usnews.com/investing/news/articles/2026-11-06/ai-boom-turns-chip-packaging-into-the-next-battleground-for-semiconductors?ref=sotkn.com) — $28B capex, Yole Group forecast, Nvidia-SPIL CoWoS financing, AMD/Taiwan investments, Powertech-Broadcom JV, Lisa Su quote. 2. [Taipei Times, “TSMC mulls making advanced AI memory chips: report,” 9 Nov 2026](https://www.taipeitimes.com/News/biz/archives/2026/11/09/2003867384?ref=sotkn.com) — TSMC 3D DRAM at Nvidia’s request; Taipei Times aggregating The Information, 6 Nov 2026; memory shortage until 2028 (Micron). 3. [VLSI.kr (Chase Na), “TSMC Weighs 3D DRAM at Nvidia’s Request, Advanced Packaging Capex Nears USD 28 Billion,” 8 Nov 2026](https://www.vlsi.kr/en/daily-silicon-2026-11-08-en/?ref=sotkn.com) — SK hynix sold out through 2029 (Q3 call); Samsung 2027 HBM fully sold (Q3 call); TSMC US-listed share move; AMD Q3 Data Center $8.5B. 4. [AMD investor relations, “AMD Reports Third Quarter 2026 Financial Results,” 3 Nov 2026](https://ir.amd.com/news-events/press-releases/detail/1303/amd-reports-third-quarter-2026-financial-results?ref=sotkn.com) — Q3 revenue $13.4B; Data Center $8.5B (+97%); Q4 guidance \~$17B. 5. [TSN Media, “Nvidia Asks All Three NVHBM Suppliers to Use TSMC 3nm,” citing Seoul Economic Daily, 18 Oct 2026](https://tsnmedia.org/nvidia-nvhbm-base-die-tsmc/?ref=sotkn.com) — NVHBM base die on TSMC 3nm; Samsung accepted; SK hynix and Micron reported as aligned; no company confirmation from any party. 6. [Rob Bulmahn, “Silicon Wafer 20200519,” 19 May 2020, Flickr / Wikimedia Commons, CC BY 2.0](https://commons.wikimedia.org/wiki/File:5C2A5953R%5F-%5F49913961083%5F%E2%80%93%5FSilicon%5FWafer%5F20200519.jpg?ref=sotkn.com) — featured cover photograph base. Attribution required by CC BY 2.0 licence.