> ## Content Index > Fetch the complete content index at: https://www.sotkn.com/llms.txt > Use this file to discover other available public pages before exploring further. # Samsung agrees to TSMC 3nm base dies for Nvidia's custom HBM - URL: https://www.sotkn.com/wire/samsung-tsmc-3nm-nvhbm-base-die-nvidia-custom-hbm-wire/ - Published: 2026-10-18T23:40:43.000Z - Updated: 2026-10-18T23:40:43.000Z - Description: Nvidia has asked Samsung, SK hynix and Micron to make the base die of its custom HBM on TSMC's 3nm process, a Korean paper reported on 18 October, and Samsung has agreed. TSMC is paid per wafer whoever wins; its 3nm lines are already its biggest node. - Author: Sean - Tags: #desk-wire `WIRE` · `SEMICONDUCTORS` · `SOUTH KOREA` · Data as at 19 Oct 2026 Nvidia wants the bottom chip of its custom memory made in one place, and that place is TSMC. On **18 October 2026** the Seoul Economic Daily reported, citing industry sources, that Nvidia has asked all three of its high-bandwidth memory (HBM) suppliers, **Samsung, SK hynix and Micron**, to make the base die of its custom **NVHBM** on TSMC's **3-nanometer** process, with the memory layers on the sixth-generation **1c** DRAM process. Samsung, which has made both layers of its HBM itself until now, accepted after an internal review. It is the first time Samsung and TSMC have worked together at the HBM manufacturing stage. None of the five companies has confirmed the report. On the [Semiconductors layer](https://www.sotkn.com/stack/semiconductors/), the logic chip under every NVHBM stack is heading to a foundry whose 3-nanometer lines are already its biggest business. ## What happened The request **Nvidia asked Samsung, SK hynix and Micron to make NVHBM base dies on TSMC 3nm and the memory dies on 1c DRAM** NVHBM, unveiled in August and built on HBM4E, moves the memory controller off the GPU and onto the base die. One process means one design behaves the same from every supplier, with less separate testing Samsung **Samsung accepted, giving up its in-house base die for this one product** It keeps its own 4nm base die for standard HBM4 and HBM4E and for other customers such as AMD, and is testing its own 2nm process as a hedge if TSMC runs short The design **Physical layer cut by 60%, for up to 30% more bandwidth and 15% less power than standard HBM4E** These are the paper's figures, not Nvidia's. Industry estimates it cites put TSMC 3nm yield above 90%, against about 60% for Samsung's comparable 2nm The capacity **3nm was 33% of TSMC's wafer revenue in the third quarter, its largest node** Two more 3nm lines at Fab 18 in Tainan start mass production in the first half of 2027 and of 2028, by the paper's account of TSMC's earnings briefing ## Why cash cares A memory stack has two kinds of chip in it. The core dies store the data. The base die at the bottom is logic, and it decides how fast data moves between the memory and the GPU. Until now each memory maker chose how to make that base die. SK hynix bought its HBM4 base die from TSMC on a 12-nanometer process, according to Korean reports cited by Taiwan's Commercial Times. Samsung made its own on its 4-nanometer foundry lines. NVHBM changes who decides. Nvidia sets the process, and the process is TSMC's. Start with who gets paid first: TSMC. Whichever memory maker wins the bigger share of NVHBM orders, the base die under each stack comes off a TSMC 3-nanometer wafer. The reports do not say whether Nvidia or the memory makers book those wafers, but either way the foundry is paid per wafer, before any stack is sold. The Commercial Times summed it up as TSMC taking the base die orders of all three suppliers. The memory makers are paid next, on the core dies, which stay theirs. Samsung's 1c DRAM lines at Hwaseong Line 17 and Pyeongtaek P2, P3 and P4 keep making the memory layers. What Samsung gives up on this product is the logic chip and a captive order for its own foundry. Its 4-nanometer base die lines sit only at Hwaseong Line 17 and part of Pyeongtaek P3, which the Seoul Economic Daily says could not absorb custom volumes like NVHBM on their own. Nvidia is paid last, in a different way. It gets one design that behaves the same from three suppliers, fewer separate qualifications, and room on the GPU for more compute, because the memory controller moved down into the stack. Here is our own arithmetic, not a company figure. UBS, as cited by the Seoul Economic Daily, projects HBM demand next year at about **61.5 billion gigabits**, up **91%**, against new supply of **54.6 billion gigabits**. The gap is about **6.9 billion gigabits**, or about **11%** of demand; the paper rounds it to about 10%. A 91% rise to 61.5 implies about **32 billion gigabits** this year. If the industry yield estimates hold, 90% against 60% means about **1.5 times** as many good base dies per wafer at TSMC as on Samsung's 2nm for the same design. And 3nm plus 2nm made up **41%** of TSMC's third-quarter wafer revenue (33% plus 8%). ![NVHBM base die ledger: three memory makers, one base die process at TSMC 3nm, and TSMC's 3nm lines already its largest node](https://storage.ghost.io/c/cd/10/cd10e222-131f-4ba4-b4a9-ca4214e8c12d/content/images/2026/10/nvhbm-base-die-tsmc-3nm-ledger-print.png) **Figure: One base die, three memory makers.** Who makes which layer of an NVHBM stack, and how full the 3nm queue already is. The 6.9 billion gigabit gap, 11%, 32 billion gigabits, 1.5 times and 41% figures are our arithmetic on the Seoul Economic Daily's 18 October reports and TSMC's 15 October results. ## The step that is still open TSMC's 3-nanometer slots. A memory maker can have its HBM4E memory dies ready and its 1c lines running, and still not ship an NVHBM stack until a base die arrives from a 3nm line it does not own. Those lines already make chips for high-performance computing and smartphones. 3nm was TSMC's largest node in the third quarter, at 33% of wafer revenue. An industry official told the Seoul Economic Daily that allocated volumes "could hit a ceiling". New capacity arrives in steps. By the paper's account of TSMC's earnings briefing, two new 3nm lines at Fab 18 in Tainan begin mass production in the first half of 2027 and the first half of 2028, with 3nm at TSMC's second Arizona plant from the third quarter of 2027 and at its second Kumamoto plant in 2028\. TSMC told investors last week that [demand for its 2nm chips is still above supply](https://www.sotkn.com/wire/tsmc-q3-2026-2nm-8-percent-demand-above-supply-wire/); the base die now joins the 3nm queue too. Ready is not paid. A memory maker earns on NVHBM only when its memory dies, a TSMC base die and Nvidia's qualification arrive together. Samsung's hedge is its own 2nm process, which it is testing for NVHBM base dies. That helps only if it passes Nvidia's checks, and the yield gap the paper cites, about 60% against TSMC's 90% or more, is why Nvidia picked TSMC first. ## The second-order read **Who gets paid.** TSMC, per 3nm base die wafer, whichever of the three memory makers wins share. The memory makers, on the 1c memory dies they still make. **Who pays.** Whoever books the base die wafers, which the reports do not name, and in the end Nvidia through what it pays for each stack. **Who waits.** Samsung Foundry, which loses a captive order on this product and is testing 2nm to win part of it back. **Stuck step.** TSMC 3nm allocation for base dies, until the new Fab 18 lines run from the first half of 2027. ## Three cautions This is one Korean newspaper citing unnamed industry sources, relayed by Reuters. Nvidia, Samsung, SK hynix, Micron and TSMC have not confirmed it, and the paper says Samsung could still make some NVHBM base dies at its own foundry. The 60%, 30% and 15% design figures, the 90% and 60% yields and the UBS demand numbers are the paper's reporting and estimates, not company disclosures. We have not seen the UBS note. There is no wafer count, contract value or start date for NVHBM volume. The 33% is TSMC's share of wafer revenue from 3nm, not a measure of spare capacity, and none of it is yet base die revenue. ## What to watch - **Confirmation**: whether Samsung, SK hynix or Micron address the base die on their third-quarter calls. - **Micron**: whether it moves its NVHBM base die to TSMC 3nm as well. - **Samsung Foundry 2nm**: any sign its base die passes Nvidia's checks as a second source. - **Fab 18**: whether the first new 3nm line starts mass production in the first half of 2027. - **HBM4E qualification**: which supplier's NVHBM ships first. *Read: [Semiconductors](https://www.sotkn.com/stack/semiconductors/), [HBM explained](https://www.sotkn.com/explained/hbm-explained/) and [who makes HBM](https://www.sotkn.com/explained/who-makes-hbm/)* --- **Get the Wire.** A free brief every day, here and in your inbox. **[Subscribe free →](https://www.sotkn.com/#/portal/signup)** Not investment advice. Do your own research. The 6.9 billion gigabit gap, 11%, 32 billion gigabits, 1.5 times and 41% figures are our arithmetic. ## References 1. [Seoul Economic Daily, "Samsung to Tap TSMC for Nvidia's Custom HBM Base Die"](https://en.sedaily.com/finance/2026/10/18/samsung-to-use-tsmc-for-base-die-in-nvidias-custom-hbm?ref=sotkn.com), 18 Oct 2026\. Nvidia's request to Samsung, SK hynix and Micron for TSMC 3nm base dies and 1c core dies; Samsung's acceptance; Samsung keeps 4nm in-house base die for standard HBM4/HBM4E and other customers including AMD; Samsung testing its own foundry as a hedge. 2. [Seoul Economic Daily, "Samsung, TSMC Join Forces to Expand Custom HBM Output for Nvidia"](https://en.sedaily.com/finance/2026/10/18/samsung-to-tap-tsmc-3-nanometer-lines-for-nvidia-custom-hbm?ref=sotkn.com), 18 Oct 2026\. Physical layer cut 60%, bandwidth up to 30%, power 15% lower; yield estimates; UBS 61.5 and 54.6 billion gigabits; Samsung base die and 1c lines; TSMC 3nm lines at Fab 18, Arizona and Kumamoto; Samsung 2nm validation. 3. [Business Standard (Reuters), "Samsung to tap TSMC technology for Nvidia's custom memory chips: Report"](https://www.business-standard.com/technology/tech-news/samsung-to-tap-tsmc-technology-for-nvidia-s-custom-memory-chips-report-126101800775%5F1.html?ref=sotkn.com), 18 Oct 2026\. Reuters relay of the Seoul Economic Daily report. 4. [Commercial Times, "Nvidia unifies HBM process, demand for TSMC 3nm heats up" (in Chinese)](https://www.chinatimes.com/newspapers/20261019000190-260202?ref=sotkn.com), 19 Oct 2026\. TSMC expected to take base die orders from all three suppliers; SK hynix HBM4 base die on TSMC 12nm moving to 3nm for HBM4E; Fab 18 P9 and P10 timing. 5. [TSMC, "TSMC Reports Third Quarter EPS of NT$29.43"](https://pr.tsmc.com/english/news/3346?ref=sotkn.com), 15 Oct 2026\. 3nm 33% and 2nm 8% of third-quarter wafer revenue.