> ## Content Index > Fetch the complete content index at: https://www.sotkn.com/llms.txt > Use this file to discover other available public pages before exploring further. # Siemens and NVIDIA cut High-NA mask compute from weeks to days - URL: https://www.sotkn.com/wire/siemens-nvidia-culitho-high-na-mask-compute-weeks-to-days-wire/ - Published: 2026-10-14T23:40:28.000Z - Updated: 2026-10-14T23:40:28.000Z - Description: Siemens and NVIDIA said High-NA photomask compute can drop from weeks to days, with 12x faster OPC. The stuck step sits beside ASML's 2027–2028 scanner shortage, not instead of it. - Author: Sean - Tags: #desk-wire `WIRE` · `SEMICONDUCTORS` · `US` · Data as at 14 Oct 2026 Siemens and NVIDIA said on **14 October 2026**, at SEMICON West in San Francisco, that GPU-accelerated computational lithography can cut full-chip optical-proximity-correction runtimes by **up to 12x**, with selected lithography simulations **10x to 17x** faster, and turnaround on the heaviest jobs from **weeks to days**. That is the software clock on High-NA EUV masks. On the [semiconductors layer](https://www.sotkn.com/stack/semiconductors/), it sits next to this morning's scanner print: [ASML said planned 2027 and 2028 tool supply will not fully meet demand](https://www.sotkn.com/wire/asml-2027-2028-supply-short-of-chip-demand-wire/). A scanner slot still has to print. The mask has to be computed first. ## What happened | Print | Figure | Source, dated | | ------------------------------------- | ---------------------------------------------------------------------------- | --------------------------------- | | Full-chip OPC | Up to **12x** faster with Calibre + NVIDIA cuLitho | Siemens, 14 Oct 2026 | | Lithography simulation | At least **10x to 17x** on selected workloads | Siemens, same day | | Mask turnaround | **Weeks to days** on the heaviest jobs | Siemens Calibre blog, 14 Oct 2026 | | cuPotential (new CUDA-X library) | **2–3x** on already GPU-optimised atomic workflows; early access | NVIDIA, 14 Oct 2026 | | Applied Materials chamber / fab twins | Up to **35x** faster chamber simulations | NVIDIA, naming Applied | | Lam etch modelling | NanoVDB **intended** in SEMulator3D; up to **30x**; targeted **end of 2026** | NVIDIA, naming Lam | | Synopsys QuantumATK / S-Device | Potential **30x** (cuEST) and **12x** (cuDSS) | NVIDIA, naming Synopsys | | KLA inspection kernel | New NPP NCC kernel **50x** vs earlier CPU versions | NVIDIA, naming KLA | NVIDIA's release is the catalogue: Applied, Cadence, KLA, Lam, Siemens and Synopsys are putting CUDA-X libraries into design, manufacturing and test. Siemens is the lithography-software print. Cadence is named at **8x** on package heat-and-stress; imec at a **30%** process-window gain. Speed-ups around the scanner, not a new EUV box. ## Why cash cares Every leading-edge AI die still needs an ASML scanner. This morning ASML said the scanners it has planned for **2027 and 2028 will not fully meet demand**. That is the hardware queue. High-NA EUV, the EXE-class tool, adds a second queue that does not ship in a crate: the photomask. Inverse lithography (ILT) and full-chip OPC on curvilinear High-NA masks have been too slow to run across a whole die, so mask shops have had to pick: restrict ILT to hotspot patches, or park a CPU farm for weeks. Siemens's 14 October print is that those jobs can now finish in days, not weeks — the difference between a High-NA layer that can be taped out on a production calendar and one that cannot. The scanner still has to exist. The mask now has a chance of arriving on the same clock. Our arithmetic, not a company figure. Take Siemens's "weeks to days" at a **14-day** CPU ILT job. At **12x**, that job is about **1.2 days**. At **17x**, about **20 hours**. At the low end of the simulation range, **10x**, about **1.4 days**. Stretch the starting point to **21 days** (three weeks) and **12x** still lands at about **1.8 days**. That is a calendar change. It does not mint extra ASML tools. It means a fab that already holds a scarce High-NA slot can iterate the mask more times before the tool sits idle. NVIDIA also gets paid here: GPUs inside the mask shop and the fab, not only inside the data centre. The 14 October release does not print a dollar figure for that cluster spend. Treat the speed-ups as the dated fact; treat the GPU bill as unstated. ## What computational lithography actually is A chip designer draws rectangles. Light does not print rectangles. Diffraction, 3-D mask effects and resist chemistry smear the image, more so at High-NA EUV, where the numerical aperture is **0.55** against **0.33** on the Low-NA NXE workhorses. [EUV lithography, explained](https://www.sotkn.com/explained/euv-lithography-explained/) is the scanner step. Computational lithography is the software step in front of it. OPC moves the edges on the mask so the wafer pattern lands where the designer meant. ILT goes further: it lets the optimiser invent curvilinear mask shapes instead of nudging a Manhattan drawing. Siemens's blog, the same day as the press note, calls computational lithography "the largest compute workload in the semiconductor production process" and lists the three bad choices without acceleration: ILT only on hotspots, CPU farms running for weeks, or slipped tape-out dates. cuLitho is NVIDIA's GPU library for that workload. Calibre is Siemens's manufacturing stack that already signs off masks. The 14 October integration is those two together. The scanner is scarce. The mask has to keep up, or the scarce tool prints yesterday's pattern. ## The second-order read **Who gets paid.** Siemens, on Calibre seats and mask-shop runtimes that can now claim full-chip ILT. NVIDIA, on the GPUs those runtimes need. Applied, Lam, KLA, Synopsys and Cadence, on the named speed-ups around the scanner, if customers turn the 14 October library list into production licences. See [who makes wafer fab equipment](https://www.sotkn.com/explained/who-makes-wafer-fab-equipment/). **Who pays.** Foundries and memory makers already in ASML's 2027–2028 queue. They pay twice: once for the tool, once for the compute that makes High-NA layers usable. Mask shops pay the electricity and the GPU capex in between. **Who waits.** Anyone reading 12x as extra wafer output in 2026\. Siemens did not print a named TSMC, Samsung, Intel or SK hynix production SLA. Lam's 30x etch model is "intended" and targeted for the end of this year, not shipping today. cuPotential is early access. **Upstream.** GPU silicon for lithography clusters — NVIDIA selling into the fab, a different offtake from a neocloud hall. No megawatt or dollar print in today's releases. **Downstream.** High-NA layers that can actually be masked on a production calendar. If the mask TAT collapses and the scanner is still short, cash still sticks with ASML on the box and with whoever holds the slot. The software win does not clear the hardware queue we [wrote up this morning](https://www.sotkn.com/wire/asml-2027-2028-supply-short-of-chip-demand-wire/). **Stuck step.** Mask compute on High-NA, now moving from weeks toward days on Siemens's verified engineering data — beside the scanner-build clock, which has not moved. Two clocks. Do not flatten them. ## Two cautions The speed-ups are vendor-verified engineering data from Siemens and NVIDIA, not a foundry's production turnaround, and not a mask-shop invoice. KLA's **50x** is against earlier CPU versions and is described as comparable with KLA's own hand-tuned kernels, so it is not a 50x jump from today's production inspection. Lam "intends" to integrate NanoVDB; the date is year-end 2026. There is no dollar figure in either primary for GPU clusters at mask shops. Do not convert 12x into a capex number. Our 14-day / 12x arithmetic is a calendar illustration from Siemens's "weeks to days" wording, not a job they timed in public. ## What would change the view - A named foundry or mask shop printing a production TAT for full-chip High-NA ILT, with a date. - Lam shipping the NanoVDB SEMulator3D build by the end of 2026, or slipping it. - A foundry saying High-NA layers are still gated by overlay, throughput or resist, not by mask compute — which would put today's 12x in the "nice" column, not the bind. - A dollar print for lithography-compute clusters, or a cut in those orders. ## What to watch - **TSMC Q3 results**, 15 October 2026 at 14:00 Taiwan time: any High-NA or mask-compute colour on the call. - **Lam's year-end 2026** SEMulator3D / NanoVDB ship date, as NVIDIA printed it. - **A named production customer** on Calibre + cuLitho, not another vendor benchmark. - **ASML High-NA recognition** in later quarters: if EXE tools sit because masks are late, today's software print was the bind; if they sit because the box itself is short, the scanner print still rules. *Read: [Semiconductors](https://www.sotkn.com/stack/semiconductors/), [EUV lithography, explained](https://www.sotkn.com/explained/euv-lithography-explained/).* --- **Get the Wire.** A free brief every day, here and in your inbox. **[Subscribe free →](https://www.sotkn.com/#/portal/signup)** Sources: [Siemens, 14 Oct 2026, Calibre + cuLitho](https://news.siemens.com/en-us/siemens-calibre-nvidia-culitho/?ref=sotkn.com) (12x OPC, 10x–17x simulation). [Siemens Calibre blog, Dr Jim Shiely, 14 Oct 2026](https://blogs.sw.siemens.com/calibre/2026/10/14/the-virtuous-cycle-of-silicon-how-siemens-is-accelerating-the-era-of-physical-ai-with-nvidia-culitho/?ref=sotkn.com) (weeks-to-days TAT). [NVIDIA via GlobeNewswire, 14 Oct 2026, 12:10 ET](https://www.globenewswire.com/news-release/2026/10/14/3380979/0/en/nvidia-and-semiconductor-leaders-advance-ai-across-chip-design-and-manufacturing-for-ai-defined-fabs.html?ref=sotkn.com) (cuPotential 2–3x; Applied 35x; Lam 30x / year-end; Synopsys, Cadence, KLA, imec). [NVIDIA Newsroom, same release](https://nvidianews.nvidia.com/news/nvidia-and-semiconductor-leaders-advance-ai-across-chip-design-and-manufacturing-for-ai-defined-fabs?ref=sotkn.com). [Wire: ASML 2027–2028 supply will not meet demand](https://www.sotkn.com/wire/asml-2027-2028-supply-short-of-chip-demand-wire/), 14 Oct 2026. Not investment advice.