AI Semiconductors: Chips, Packaging and Bottlenecks

Chips, packaging and HBM as the semiconductor layer of the AI Stock Map — bottlenecks, roster, and falsifiable flips.

China AI compute capacity chart — Second Order by TKN
AI semiconductor compute capacity chart

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Chips design the AI boom. Packaging and memory often decide who ships. This layer covers design, foundry, advanced packaging (including CoWoS), HBM, and equipment — and where rent sits when one step is full.

Status: Tightening · Updated: 2026-09-12

Investor read: Finished AI accelerators need more than a clever die. They need foundry slots, HBM stacks, and advanced packaging capacity. When CoWoS-style lines or HBM allocation bind, pricing power and lead times show up there — even if wafer starts look fine. Neighbours: Power, Servers, Hyperscalers.

On this page

What this layer is

The semiconductors layer is the hardware path from idea to shippable AI module:

  1. Design — GPU / accelerator architecture (and increasingly custom silicon).
  2. Foundry — printing compute dies on leading process nodes.
  3. Memory — especially HBM stacks that sit next to the GPU.
  4. Packaging — joining compute and HBM (CoWoS-style and peers).
  5. Equipment — tools that make steps 2–4 possible (lithography, etch, test, grind).

If any scarce step is full, finished GPUs wait in a queue. That is bottleneck economics, not a slogan.

Where the rent sits

Second-order readers ask: which sub-layer is capacity-constrained, not only demand-constrained?

Sub-layer Role Why it can bind
Design Defines the accelerator Competition and custom ASICs shift share; rarely the physical gate alone
Foundry Prints dies Leading-edge capacity and yield matter; still waits on packaging/HBM to ship modules
HBM Fast memory next to the GPU Stack supply and allocation can ration finished AI parts
Packaging (CoWoS-style) Joins die + HBM Scarce slots became a famous finish-line gate in recent cycles
Equipment (WFE / test) Tools for fabs and packaging Long lead times; expands capacity with a lag

Deep explainers: CoWoS, Explained · HBM, Explained.

Sub-layer splits

Split What to watch Typical signal
Design vs manufacturing Who captures ASP vs who captures volume Designer margins vs foundry/OSAT utilization
HBM vs commodity DRAM AI modules need HBM bandwidth Memory makers’ HBM mix and allocation comments
Packaging vs wafer starts Modules need both Packaging lead times vs wafer commentary
Logic tools vs memory tools Different tool baskets WFE order mix and backlog

This is a map of where cash can stick, not a ranking of names to buy.

Short roster

Examples of exposure only — not recommendations. Always verify listing and access for your jurisdiction.

Role Examples
Accelerator design NVIDIA, AMD, Broadcom
Foundry / advanced packaging TSMC
HBM / memory SK Hynix, Samsung, Micron
Wafer-fab equipment ASML, Applied Materials, Lam Research, KLA
Test / grind / related tools Advantest, Disco

International access often runs through US listings, ADRs, or local lines. Tax and custody rules differ by country — check before you trade.

What would change the view

Falsifiable flips (any one is enough to revisit Tightening):

  • Credible, sustained packaging capacity growth that clears queues for leading AI modules.
  • HBM supply catching allocated demand so memory stops rationing shipments.
  • Clear demand pause from hyperscalers / neoclouds that frees slots without new supply.
  • A process or architecture shift that reduces CoWoS/HBM intensity per unit of useful compute.

We would move toward Stable or Loosening only with dated evidence — filings, capacity tours, or consistent lead-time relief — not a single headline.

Who writes this

Second Order by TKN maps constraints for international readers. Educational only.

FAQ

Is this a buy list?

No. It is a map of exposure and constraints. Not investment advice. Do your own research.

Why do packaging and HBM matter as much as the GPU brand?

Because a die that cannot be packaged with HBM does not ship as a finished AI accelerator. The scarce finish-line step sets lead times for the whole stack.

What does Tightening mean here?

Capacity or allocation is binding relative to demand — recently that has meant CoWoS-style packaging and HBM more than “any wafer anywhere.”

How do international investors get exposure?

Often via US-listed names, ADRs, or local listings linked to foundry, memory, and equipment. Always verify ticker, ADR ratio, and tax treatment for your jurisdiction.

Start with CoWoS explained and HBM explained, then return to the The Stack for neighbouring layers.

Not investment advice. Do your own research.
Last updated: 2026-09-12 · Second Order by TKN