CoWoS, Explained: The Packaging Step That Limits AI GPUs
CoWoS packages an AI GPU next to fast memory. When demand rises, scarce packaging slots become the paid bottleneck — and finished dies wait.
CoWoS is a way to package AI chips so a powerful GPU sits next to very fast memory. Without that packaging step, many top AI accelerators cannot ship as finished parts. When AI demand rises, scarce CoWoS-style capacity becomes a bottleneck that suppliers get paid to relieve.
In short: CoWoS stands for chip-on-wafer-on-substrate. It is the factory step that joins a compute die and HBM stacks into one dense module. A GPU can be finished at the wafer level and still not be shippable, because packaging is the real finish line.
What is CoWoS?
CoWoS — chip-on-wafer-on-substrate — is an advanced packaging process that places a compute die and its HBM stacks onto a shared base, then onto a substrate, producing one finished accelerator module. It exists because an AI GPU needs memory close enough to feed it, and ordinary board-level assembly cannot put them that close.
An AI GPU is not only one bare chip. It needs high-bandwidth memory placed very close so data can move quickly. CoWoS places the compute die and HBM stacks onto a special base — an interposer or related structure — and then onto a substrate. The result is a module that can move huge amounts of data without waiting on slow, distant memory.
Think of it as building a tiny city on one board. The GPU is the factory. HBM is the warehouse next door. CoWoS is the construction method that puts them on the same street.
TSMC and CoWoS: why one company defines the queue
CoWoS is TSMC's branded advanced-packaging family, which is why "CoWoS capacity" and "AI GPU supply" are so often used as if they were the same sentence. Other foundries and OSATs run comparable advanced packaging, but CoWoS is the name attached to the specific queue that leading AI accelerators sit in.
That concentration is the point. When one company owns the dominant version of the scarce step, its capacity decisions set the industry's finish-line throughput — and its customer priority list decides who ships first.
The family is not one process. Three variants matter for reading supply:
| Variant | What it uses | Why it matters |
|---|---|---|
| CoWoS-S | A silicon interposer | The classic, highest-density route; hardest to scale because interposer size is limited |
| CoWoS-R | An organic redistribution layer | Cheaper and easier to scale, lower density |
| CoWoS-L | A hybrid with local silicon bridges | The route for very large multi-die packages; where new capacity is going |
When commentary says CoWoS is sold out, it usually means the specific variant the newest accelerators need — not all three. A shift in the mix from -S toward -L changes effective capacity without changing the headline number, which is a common source of confused reading.
Two consequences follow for anyone reading the trade:
- Capacity announcements are variant-specific. "CoWoS capacity doubles" means little until you know which variant, and whether the accelerators in demand can use it.
- Taiwan concentration is a real single point. Most of this capacity sits in one country with one dominant supplier — see the Taiwan market hub for the country view and the wider foundry and packaging set.
Treat CoWoS as the packaging bottleneck layer, not as a company call.
Why does packaging matter as much as the chip design?
People often talk only about the GPU brand. The design matters and the manufacturing node matters. Packaging still sits on the critical path.
The simplified production path:
- Designers create the accelerator architecture
- A foundry prints compute dies on wafers
- Memory makers build HBM stacks
- Advanced packaging joins compute dies and HBM into one module
- Finished GPUs go into servers and rented clusters
If step 4 is full, finished GPUs stay scarce even when wafer starts look fine. That is why CoWoS became a household word among supply-chain readers. It is the finish line where compute and memory meet.
Why do finished GPUs wait?
People hear "GPU shortage" and picture empty shelves. The deeper read is usually a mismatch of stages.
A die is the bare chip cut from a wafer. Advanced packaging takes that die, places high-bandwidth memory next to it, and builds a module that can ship into a server. When packaging capacity is full, wafers and dies pile up. The GPU is made at the wafer level but is not ready for a board.
Think of a kitchen that can cook many steaks but has only a few plates. The food is ready. Service still waits on plating. Packaging is the plating step for high-end GPUs.
Illustrative shape, not a forecast: if a maker can produce 100 dies in a period but package only 70 of them in the same advanced process, roughly 30 finished dies wait.
This is why news about packaging queues matters more than a raw wafer count.
How does the bottleneck actually work?
Advanced packaging needs special tools, clean processes, and skilled capacity. Expanding a line takes time and capital, and demand for AI accelerators grew faster than packaging could expand.
The mechanism is simple:
- Each leading AI GPU consumes packaging slots
- A few large buyers book multi-year allocations
- Remaining slots for everyone else shrink
- Lead times stretch
- Upstream chip designs queue to become shippable products
Raising prices or prioritising key customers is how scarce capacity gets rationed. Expansion helps, but new tools do not appear overnight. The scarce step earns pricing power until capacity catches demand, or demand cools.
What a sold-out headline does and does not mean
A queue does not mean the whole industry stops. It means the scarce style of package is booked. Simpler packages may still move and mid-tier parts may still ship. The bottleneck hits hardest where the densest packages are needed.
That is why the same news cycle can sound bullish for packaging suppliers and tight for buyers who need the top tier.
When reports say packaging is sold out or lead times stretch, they usually mean four things at once: demand for dense AI packages is high, the tools and clean rooms for that style are limited, memory and interposer pieces must arrive in sync with the compute die, and final test capacity must keep up afterwards.
Who sits around the packaging step?
| Position | Who | Why they matter |
|---|---|---|
| Upstream | Wafer fabs, memory makers, tool vendors | Feed the package with dies, stacks, and capacity |
| The step | Foundry packaging arms, OSATs | Own the scarce slot |
| Downstream | Board makers, server OEMs, hyperscalers, neoclouds | Wait on finished modules |
Chip designers such as NVIDIA need packaging to ship many of their top AI GPUs. HBM suppliers — SK Hynix, Samsung, Micron — feed the memory stacks that CoWoS attaches.
Packaging is a bridge. If either side is late, the package slot sits empty or gets reshuffled. If the slot is late, both sides wait. Buyers' capital expenditure plans assume packaging slots deliver on schedule, and delays ripple into rented GPU capacity.
What would change this view?
The tight read on packaging loosens if:
- New advanced packaging lines qualify and reach stated throughput
- Alternative packaging routes take meaningful share from the scarce style
- A mix shift toward CoWoS-L raises effective slots faster than demand for them
- Substrate and HBM supply arrive matched rather than staggered
- Accelerator designs shift toward fewer packaging slots per unit of compute
- GPU demand cools enough that booked allocations free up
It stays tight while lead times stretch and buyers outside the top tier still report allocation.
Practical takeaways
- Wafer output and packaging output are different clocks
- "Sold out" applies to the scarce package variant, not all packaging
- Ask which CoWoS variant an announcement refers to before believing the number
- Memory and substrates must arrive matched or the slot is wasted
- Name the scarce step rather than saying "chips are short"
FAQ
What does CoWoS stand for?
Chip-on-wafer-on-substrate. It is an advanced packaging family that places a compute die and HBM stacks onto a shared base and then onto a substrate.
Who makes CoWoS packaging?
CoWoS is TSMC's branded packaging family, and TSMC runs the dominant share of it. Other foundries and OSATs offer related advanced packaging routes under different names.
What is the difference between CoWoS-S, CoWoS-R and CoWoS-L?
CoWoS-S uses a silicon interposer and gives the highest density. CoWoS-R uses an organic redistribution layer and is cheaper to scale. CoWoS-L uses local silicon bridges in a hybrid structure and is the route for very large multi-die packages.
Why is CoWoS a bottleneck for AI GPUs?
The tools and clean rooms are specialised and slow to expand, while each leading accelerator consumes packaging slots. Demand grew faster than capacity.
Does a packaging shortage mean no GPUs at all?
No. It means the densest package style is booked. Simpler packages and mid-tier parts can still ship.
Is packaging the same as the HBM shortage?
No, they are neighbouring gates. Packaging joins the stack to the die — see HBM explained. Either can bind, sometimes at different times.
