What Is CoWoS? Chip-on-Wafer-on-Substrate for AI GPUs

CoWoS is chip-on-wafer-on-substrate — TSMC’s advanced packaging family that places a compute die and HBM stacks on a shared base, then onto a substrate, so an AI GPU can ship as one finished module.

The money link: who gets paid when AI accelerators need matched packaging, where slots and variants bind the chain, and how to tell a land plan or capacity slide from finished modules that actually leave the line. Mechanism — not a scorecard of names.

EXPLAINEDLast reviewed: 03 Oct 2026Next review: after Chiayi comment close (~24 Oct) or next TSMC earnings / CoWoS capacity update

Education only. Not investment advice. Do your own research.

What is CoWoS?

CoWoS — chip-on-wafer-on-substrate — is a 2.5D packaging process that puts logic chiplets and high-bandwidth memory on one interposer-class base, then onto a substrate. Ordinary board assembly cannot put memory that close. AI GPUs need the short path so data can feed the die without waiting on distant host DRAM. See the semiconductors stack for how this packaging gate sits next to foundry and memory.

TSMC’s public CoWoS technology page describes the platform as the foundation for HPC and AI products that integrate multiple SoCs with HBM stacks. Volume production of the family dates to 2012. Think of the GPU as the factory and HBM as the warehouse next door — CoWoS is the construction method that puts them on the same street.

CoWoS-S vs CoWoS-R vs CoWoS-L: what is the difference?

The family is not one process. Three variants matter when you read supply commentary. A “sold out” headline usually means the scarce style the newest accelerators need — not every CoWoS line.

TSMC recommends CoWoS-L or CoWoS-R when the interposer needs to exceed the CoWoS-S size band. DIGITIMES Research (Oct 2024) estimated that by end-4Q 2025 CoWoS-L would be about 54.6% of TSMC’s CoWoS capacity mix, with CoWoS-S about 38.5% and CoWoS-R about 6.9% — a dated research estimate, not a company filing. A mix shift from -S toward -L can change effective slots without changing a vague “CoWoS capacity” headline.

Why does CoWoS bind AI GPUs?

People often talk only about the GPU brand and the wafer node. Packaging still sits on the critical path. The simplified chain: designers create the accelerator; a foundry prints dies; memory makers build HBM; advanced packaging joins die and stacks; finished modules go into servers and cloud fleets. If the join step is full, finished GPUs stay scarce even when wafer starts look fine.

On TSMC’s Q2 2026 earnings call (16 Jul 2026), Chairman C.C. Wei said packaging capacity was “so tight that now it’s limiting my customers’ growth,” and that the company welcomes alternative packaging routes so front-end wafers can still become finished products. That is the mechanism in one sentence: the attach step can throttle shippable AI GPUs independently of front-end wafer counts.

Land and plant plans ≠ working CoWoS slots

A science-park expansion notice is a land gate, not a packaging-slot print. On 23 Sep 2026 Taiwan’s National Science and Technology Council (NSTC) opened Chiayi Science Park’s Phase II expansion to public comment — positioning heterogeneous packaging and related AI industry space on Taiwan Sugar lease land. Press puts the area near 198–198.65 hectares and the comment window close near 24 Oct. Liberty Times supply-chain sources via Taipei Times say TSMC wants five more advanced packaging plants at Chiayi (toward 10 total) — that plant count is reported, not an NSTC confirmation. Markets door: Chiayi packaging land (Oct 2026).

Hectares on a consultation form do not print working packages. After land and EIA come construction, tool-in, and yield. Parallel overflow: MOEA’s Bureau of Industrial Parks (22 Sep 2026 English) framed SPIL’s NT$100bn Yunlin CoWoS plant (ops 2028) — an overflow packager clock, not Chiayi slots. The stuck step remains CoWoS-class packaging capacity.

How much CoWoS capacity is there — and who discloses what?

TSMC does not publish a single official “CoWoS wafers per month” figure in its earnings release. What is checkable from primary IR is CapEx intent and qualitative tightness. What is checkable from dated trade research is estimated throughput bands. Keep those two layers separate.

TrendForce’s 15 June 2026 note also said the severe global 2.5D packaging shortage may begin moderating in 2027 — narrowing the gap is not the same as closing it inside 2026. DIGITIMES Research (Oct 2024) had earlier put TSMC above 65,000 wafers/month by end-2025, with Amkor and ASE combined near 17,000 — useful as a prior checkpoint, not as today’s realised output. Markets door when capacity is the story: TSMC CoWoS capacity and the Taiwan market hub.

Who gets paid when CoWoS is scarce?

TSMC owns the branded CoWoS family and the dominant share of leading AI attach capacity. On the same July 2026 call, management said about 10–20% of the US$60–64bn 2026 CapEx budget goes to advanced packaging, testing, mask making, and others — a bucket, not a pure CoWoS line item. OSATs such as ASE (including SPIL) and Amkor add CoWoS-class or CoWoS-like capacity under different commercial names.

When slots are tight, two synchronisation problems appear. If HBM arrives late, a reserved packaging slot may slip. If packaging is late, HBM inventory sits. Either way, finished modules delay. CapEx at hyperscalers and fleet growth at neoclouds show up here with lag. Neighbouring gates: HBM explained, EUV lithography, and who makes AI chips.

Early validation is not volume. On 28 Sep 2026 SK hynix said it won TSMC Partner of the Year for validating HBM5 on CoWoS from early design (newsroom) — attach colour, not shipment. Wire: SK hynix HBM5–CoWoS validation. If packaging eventually eases, the stuck step can move — see Where does the stuck step move?.

How do you read a CoWoS capacity announcement?

Four questions separate a plan from supply: variant (S, R, or L?), timing (when does meaningful output arrive?), units (wafers per month, annual wafers, CapEx aspiration — or hectares?), and commitment (are GPU customers already under allocation?). Without those four, “more CoWoS” is a slogan. Named future land or plant paths are not today’s slot in a GPU package. Glass substrates and other alternatives are a separate clock — TSMC said on the July 2026 call that CoWoS is still the majority path and that a glass pilot needs about another year to mature for customer production.

Common misconceptions

• People assume CoWoS is the same as any advanced packaging. Actually CoWoS is TSMC’s branded family (S / R / L). Other foundries and OSATs run related 2.5D routes under different names.
• People assume a land notice or capacity slide means open supply this quarter. Actually check variant, year of meaningful output, units, and whether customers are already allocated — hectares are not yields.
• People assume CoWoS and HBM are the same bottleneck. Actually they are neighbours. Either one can bind, often on different clocks — and HBM5–CoWoS validation is not volume.
• People assume sold-out packaging means no GPUs ship at all. Actually the densest style is booked; simpler packages and mid-tier parts can still move.

Not investment advice. Do your own research.

FAQ

Related terms

• HBM — memory twin that feeds the package.
• HBM vs DDR5 — nearby lane vs board memory.
• EUV lithography — patterning step upstream of advanced logic.
• Hyperscaler — CapEx dial that sets AI packaging demand with lag.
• Neocloud — specialist GPU cloud that feels packaging scarcity as delayed hours.
• Who makes AI chips — players along the accelerator bill of materials.
• Neoclouds stack — specialist GPU capacity layer above scarcity.

Sources