TSMC weighs CoWoS price rises of up to 20% as AI chip tests lengthen

WIRE · SEMICONDUCTORS · TSMC · Data as at 27 Oct 2026

The queue for AI chip packaging is getting a price tag. On 27 October 2026, Taiwan's Commercial Times reported, citing supply chain sources, that TSMC and the outsourced packaging and test houses are preparing another round of CoWoS price rises of 10% to 20%, with some packaging lead times already stretching. TSMC has not confirmed the figure. The same report says chip testing is taking longer, equipment lead times have stretched to six to eight months, and TSMC placed this year's tool orders at existing prices without asking for its usual discounts. On the semiconductors layer, the step that sets the price has moved from the wafer to the package and the test bench.

What happened

Why cash cares

CoWoS is the step where an AI processor and its stacks of high-bandwidth memory are joined on one base before the package goes onto a board. Almost every large AI accelerator passes through it, and TSMC does most of it. When a supplier at that step can raise prices by up to a fifth and still sell out, the cost moves to the people who need the step, not the people who own it.

Capacity is growing fast. Analysts quoted by Commercial Times put TSMC's monthly CoWoS output above 130,000 wafers in 2026, aiming for 200,000 in 2027, about 54% more (our arithmetic). Goldman Sachs has a steeper path, from about 106,000 a month in 2026 to about 227,500 in 2027. Either way, the price rise says buyers still want more than that.

The test numbers explain part of the gap. If each Rubin chip spends about seven times as long in final test as a Hopper chip did, the same test floor handles far fewer chips a day. More packaging lines do not fix that on their own. The shop also needs more testers, more sockets and more floor space, ordered from toolmakers who now quote up to eight months.

Figure: test time and tool lead times are rising faster than packaging capacity. Figures from Commercial Times and Liberty Times as carried by TrendForce on 27 October 2026, and Nomura's test-time estimate; the capacity growth rate is our arithmetic.

The second-order read

Who gets paid. TSMC first, since a higher CoWoS price lands straight in its packaging revenue. The packaging and test houses that take overflow work, which the report says are preparing the same 10% to 20% rise. The toolmakers, who for once are selling to TSMC at full price. Makers of chip testers and test sockets gain the most from longer test times, because longer tests mean more machines for the same number of chips.

Who pays more. Nvidia, AMD and the designers of custom AI chips, who buy both the wafer and the package. They can pass some of it to the cloud companies that buy their systems. We saw the same pull when Nvidia paid $1.1 billion for US test capacity last week. AMD and Nvidia are both now putting money into substrates, packaging and testing, Digitimes reported on 27 October.

Who waits. Smaller chip designers and late orders. When customers order on delivery date rather than price, the biggest buyers with the longest commitments get their slots first.

Stuck step. The busiest station inside a packaging plant. Toolmakers told Commercial Times that a new advanced packaging plant takes about three years from groundbreaking to running its bottleneck stations at full load. Output is set by lithography, developing and die-attach steps, and the bottleneck shifts as processes change. A finished building with tools moved in still has to be tuned and qualified before it adds supply.

Two cautions

The 10% to 20% figure comes from supply chain sources quoted in one newspaper. TSMC has not confirmed it, and the final rise could be smaller, apply only to some customers, or come in stages.

A higher price is not only a sign of scarcity. Bigger packages cost more to make. TSMC is already producing packages five times the size of a standard chip exposure and developing nine and fourteen times sizes, so part of any rise may reflect more silicon and more steps per package.

What would change the view

• TSMC confirming or denying the CoWoS rise, or citing it on its next earnings call.
• Monthly CoWoS output reaching the 200,000 wafer target early, which would ease the price power.
• Tool lead times falling back towards three to six months, which would show the toolmakers have caught up.

What to watch

• TSMC's monthly sales, for whether packaging is lifting revenue faster than wafers.
• Test equipment makers' next results, for orders tied to longer AI chip tests.
• Nvidia's and AMD's next gross margins, for how much of the higher cost they absorb.

Read: the semiconductors layer and CoWoS explained

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Not investment advice. Do your own research. The capacity growth rate is our arithmetic from analyst estimates.

References

1. Commercial Times, "台積CoWoS傳喊漲上看2成" (TSMC CoWoS reportedly to rise up to 20%), 27 Oct 2026
2. TrendForce, "TSMC Reportedly Eyes 20% CoWoS Price Hike, Skips Equipment Price Renegotiations Amid AI Demand Surge", 27 Oct 2026
3. Investing.com, "TSMC to raise advanced chip packaging prices by up to 20%, report says", 26 Oct 2026
4. Digitimes, "AMD, Nvidia target substrate capacity amid 4x expansion constraints", 27 Oct 2026