The Stack
Semiconductors — Chips, Packaging and the Stuck Step
Status Tightening as of 23 Sep 2026: CoWoS-L path through 2028, Baipu tool validation, and HBM stack/bond — packaging clears before any wafer story finishes the module.
No layer articles yet. The standing map below still applies.
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Semiconductors turn AI designs into shippable modules: design, foundry wafers, HBM stacks, advanced packaging, and the tools that clear those lines. This Stack layer tracks who gets paid when finished accelerators wait — and which step is stuck.
Status: Tightening · Updated: 2026-09-23
Investor read: In this layer, cash often sticks first with packaging capacity, HBM attach, and the tools or materials that clear those lines — not with “any wafer start.” The stuck step is CoWoS-class packaging (CoWoS-L still the mainstream path through 2028 per TrendForce) plus the HBM stack and bond path. Front-end wafer commentary can look fine while finished AI modules wait.
On this page
Function
The semiconductors layer is the hardware path from idea to shippable AI module:
- Design — GPU / accelerator architecture (and custom ASICs).
- Foundry — printing compute dies on leading process nodes.
- Memory — especially HBM stacks that sit next to the accelerator.
- Packaging — joining compute and HBM (CoWoS-class and peers).
- Equipment / materials — tools that make foundry, stack, and package steps possible.
If any scarce finish-line step is full, finished accelerators wait. That is bottleneck economics, not a slogan. Teaching cuts: CoWoS explained, HBM explained, HBM vs GDDR, and Who makes HBM.
In the AI build chain this layer sits upstream of neoclouds and hyperscalers: packaging and HBM decide when chips can ship; fleets and platforms decide when those chips become billable capacity.
Who gets paid here is whoever clears the scarce attach or stack step. Who waits is the designer or buyer with wafers that cannot yet become modules.
Stuck step
The popular story says the bind is always “not enough wafers.” Wafer starts still matter. But the cash bind inside this layer is usually packaging capacity, HBM stack supply, and the tools that expand those lines — often ordered before the capacity they enable.
1. CoWoS-class packaging. On TSMC’s Q2 2026 earnings call (16 Jul 2026), Chairman C.C. Wei said packaging capacity was “so tight that now it’s limiting my customers’ growth.” That is a primary IR statement: the attach step can throttle shippable AI modules even when front-end commentary sounds fine.
2. Architecture path through 2028. TrendForce (18 Sep 2026) keeps TSMC’s CoWoS-L as the mainstream advanced-packaging platform for AI chips through 2028, ahead of Intel’s EMIB-T on technology maturity and yield. Larger GPU and ASIC packages that outgrow a single large interposer queue for CoWoS-L’s local silicon bridges. Our Wire on CoWoS-L through 2028 reads that as the packaging stuck step still setting the short clock.
3. Tools and materials before volume lines. On 21 Sep 2026, Kaohsiung’s Baipu Industrial Park broke ground with TSMC as anchor — framed as a modular Mini-Loop validation hub for back-end equipment and materials, not another CoWoS volume fab, with a stated 25–50% validation-efficiency aim and operations expected Q4 2029 (Reuters / Commercial Times / TrendForce as reported). Our Markets Pulse on Baipu CoWoS validation maps who gets paid as suppliers that clear that gate and OSATs beside it — while the near ramp still runs through existing packaging lines.
4. HBM stack and bond. A finished module also needs HBM cubes bonded and attached. Tools such as thermal-compression bonders are ordered ahead of the stacking capacity they enable — the same “tools before wafers” clock in our Analysis Hanmi memory stuck step and the long-clock map in Where does the stuck step move.
So the stuck step, named plainly: CoWoS-class packaging capacity (CoWoS-L path still binding through 2028) plus HBM stack/bond clearance — with tools and materials that unlock those lines getting paid before “any wafer” story finishes the module.
Role companies
Roles only — not a leaderboard, not a buy list.
| Role | Examples | What they do in this layer |
|---|---|---|
| Accelerator design | NVIDIA, AMD, Broadcom (and custom ASIC teams) | Define the die and package demand; wait if packaging/HBM slots bind |
| Foundry / advanced packaging | TSMC (CoWoS-class) | Print dies and join them with HBM; own much of the finish-line gate |
| HBM / memory stacks | SK hynix, Samsung, Micron | Build DRAM stacks that sit beside accelerators |
| Packaging / stack tools & materials | Hanmi (TC bonders) and back-end tool/material OEMs | Clear stacking and packaging capacity; often paid before volume lines expand |
| OSAT / test adjacent | ASE, SPIL (and peers) | Add packaging and test capacity beside foundry gates |
Always verify listing, ADR, and tax treatment for your own jurisdiction. Names here map roles. They are not recommendations.
Links
Explained
Wire & Analysis
- Wire: CoWoS-L mainstream through 2028
- Analysis: Hanmi memory stuck step
- Analysis: Where does the stuck step move
Markets
Topic hubs & sibling Stack layers
FAQ
Is this a buy list?
No. This is a map of roles and constraints. Not investment advice. Do your own research.
Why is status Tightening on 2026-09-23?
Because dated evidence still shows packaging and HBM attach as the finish-line bind: TrendForce keeps CoWoS-L mainstream through 2028 (18 Sep 2026); TSMC’s chairman said packaging was limiting customer growth (16 Jul 2026); Baipu’s Mini-Loop (21 Sep 2026) is a validation hub aimed at tool/material clearance, not near-term wafer-start relief. We would move status only with dated queue-clearance evidence.
Why care about packaging if wafer starts look fine?
Because a die that cannot be packaged with HBM does not ship as a finished AI accelerator. Packaging and stack attach can throttle modules independently of front-end wafer counts.
How is this different from the neocloud layer?
Semiconductors decide when modules can ship. Neoclouds turn delivered chips and megawatts into billable fleet hours. The stuck steps differ: CoWoS/HBM/tools versus utilization, power delivery, and customer concentration. See Neoclouds.
Do tools get paid before packaging capacity expands?
Often yes. Tools and materials are ordered and qualified ahead of the lines they enable — the Baipu Mini-Loop thesis and the Hanmi TC-bonder clock are both “tools before wafers” stories, not tip sheets.
What would change the view
- Credible, sustained CoWoS-class packaging capacity growth that clears queues for leading AI modules — with lead times and allocation language easing across multiple dated prints.
- HBM stack supply catching allocated demand so memory stops rationing finished shipments, and bonder/tool order urgency cools for several quarters.
- A clear demand pause from hyperscalers / neoclouds that frees packaging and HBM slots without new supply.
- A process or architecture shift that measurably reduces CoWoS-L / HBM intensity per unit of useful compute (including real EMIB-T spillover beyond single-customer tests).
Sources
- TrendForce, 18 Sep 2026 — CoWoS-L mainstream AI packaging through 2028. Link
- Reuters, 21 Sep 2026 — Taiwan Baipu advanced packaging park groundbreaking; TSMC validation buildings; ops expected Q4 2029 (as reported). Link
- Commercial Times / TrendForce, 21 Sep 2026 — Mini-Loop 25–50% validation-efficiency aim (Jun He stated aim). Link
- TSMC Q2 2026 earnings call, 16 Jul 2026 — C.C. Wei packaging capacity limiting customer growth. Link
- TSMC — CoWoS technology page (S / R / L). Link
Not investment advice. Do your own research.
Last updated: 2026-09-23 · Second Order by TKN