Micron plans to stack HBM on top of AI chips from 2028
Micron showed a roadmap with vertical HBM, memory stacked straight onto the processor, aimed at 2028, and said memory supply will not catch up with demand. Heat and bonding now set the pace.
WIRE · SEMICONDUCTORS · MEMORY · Data as at 25 Oct 2026
Micron wants to move AI memory from beside the chip to on top of it. At a technology webinar on 21 October 2026, president and chief technology officer Scott DeBoer showed a roadmap with vertical HBM, memory stacked straight onto the processor, aimed at volume production in 2028, with three generations planned through 2030. He also said Micron does not see memory supply and demand coming back into balance: "We actually do not see a time when it comes into balance." On the semiconductors layer, the next fight over AI memory is about heat and bonding, not just more wafers.
What happened
21 October 2026 · Micron technology webinar
Vertical HBM targeted for volume production in 2028
The DRAM stack sits directly on the compute die, joined by hybrid copper bonding, the shortest path between memory and processor. Micron expects it to sit alongside ordinary HBM stacks in many systems
The standard line
HBM4E in 2027, HBM5 in 2028, HBM5E in 2029, HBM6 in 2030
HBM4 in 36GB 12-high stacks entered high-volume production in March 2026. HBM4E is the first generation where Micron offers custom parts, and it moves to a base die made by a foundry instead of its own
The nodes
1-delta DRAM and 400-plus-layer NAND both ramp in late 2027
The 1-delta DRAM node starts in Boise with a mid-20% density gain and is built for HBM5 and vertical HBM. NAND skips a generation name to G11, with twice the bit density of today's G9
The supply line
"The trade ratios continue to increase"
DeBoer said each new memory type uses more wafer per bit than the last, and that supply stays tight for at least two years
Why cash cares
Today an AI accelerator is surrounded by HBM stacks that sit next to it on a silicon interposer, a wiring layer underneath. Bandwidth is limited by how many stacks fit around the edge of the chip and how far the signals travel. Vertical HBM puts memory on the chip itself, so the connection runs straight down instead of sideways. Micron's slides sell this as more bandwidth per watt and more tokens per watt, which is what inference buyers pay for.
The catch is physical. An AI processor is one of the hottest parts in a data center, and stacking memory on top puts a blanket over it. BNP Paribas analyst Karl Ackerman wrote that vertical HBM "inhibits the cooling of the processor", which is why he expects it to be used together with normal HBM rather than replacing it. Micron's own slides list "advanced thermals" and "thermally aware design" as conditions for the product, and the company named no launch customer, volume or price.
The wafer point matters sooner. Micron has said HBM3E already uses about three times the wafer input of ordinary DDR5 for the same capacity. If each step up the ladder uses more, then every new HBM generation takes supply away from the DRAM that goes into normal servers, PCs and phones, even before new fabs open. That is the reason Micron, the smallest of the three big memory makers, says it sees no point at which supply catches up. We covered how Micron has already locked up most of its 2027 memory output.
Figure: Micron's memory moves from beside the chip, to a custom base die, to on top of the chip within four years. Targeted high-volume production years from Micron's 21 October 2026 technology webinar. Micron says timing is directional and subject to change.
The second-order read
Who gets paid. Foundries first. From HBM4E, Micron joins rivals in buying the base die, the logic layer at the bottom of each stack, from a foundry, reported to be TSMC at a 3nm-class process. We saw the same move when Samsung agreed to TSMC base dies for Nvidia's custom HBM. Next, makers of hybrid bonding tools, since vertical HBM, G11 NAND and Micron's later DRAM nodes all depend on bonding wafers or dies together. See how hybrid bonding works and our Wire on why Besi's HBM orders still come from older bump tools.
Who pays. Buyers of ordinary memory. Rising wafer use per bit means less DRAM and NAND for everything else, so server, PC and phone makers keep paying higher contract prices while AI parts get priority.
Who carries the risk. Micron and the chip designers who sign up. Vertical HBM only works if memory and processor are designed together from the start, so a customer that commits is tied to one memory supplier for that chip. If heat removal or bonding yields fall short, the 2028 date slips and the design work has to be redone.
Stuck step. Heat and bonding at volume. Memory makers can already make the DRAM dies. What sets the pace is getting heat out of a hot processor through a memory stack, and bonding the two at fine pitch with enough good units to sell.
Two cautions
This was a roadmap, not a sales announcement. Micron gave no customers, volumes or prices for vertical HBM, and its slides say timing and performance targets are directional and subject to change.
Several big steps land in the same window. HBM4E, 1-delta DRAM and G11 NAND all ramp in 2027, alongside first output from Micron's new Idaho fab. A slip in one can delay the others.
What would change the view
- A named customer for vertical HBM, which would turn a slide into a design contract.
- Rivals showing their own memory-on-logic plans, which would make this an industry path rather than a Micron bet.
- Memory contract prices easing in 2027, which would undercut the claim that supply never catches up.
What to watch
- SK hynix and Samsung third-quarter results around 28 and 29 October, for HBM sales and any comment on memory stacked on logic.
- HBM4E qualification news in 2027, for which foundry makes Micron's base die.
- Bonding tool orders, as a sign that vertical stacking is moving from labs to factories.
Read: the semiconductors layer and how memory process tools work
Get the Wire. A free brief every day, here and in your inbox. Subscribe free →
Not investment advice. Do your own research.
References
- Micron, "Technology and products leadership for the AI era", webinar slides, 21 Oct 2026
- Blocks and Files, "Micron skipping planned NAND generation", 22 Oct 2026
- VLSI Korea, "Micron Deep Dive: The Technology Webinar, Decoded", Oct 2026
- TokenPost, "Micron Maps HBM Roadmap Through 2030, Sees Memory Imbalance for Two Years", 24 Oct 2026
