Who Makes AI Chips

EXPLAINED · Players · Last reviewed: 25 Sep 2026 · Next review: after next major foundry/packaging/HBM capacity note

Who makes AI chips is the roles map for AI accelerators: which firms design the GPU or ASIC, which foundries fabricate the logic wafers, which partners attach logic beside HBM on advanced packaging, and which memory makers supply the stacks.

For investors on the Semiconductors layer, the useful question is which role gets paid when AI CapEx binds scarce wafers, packaging, and HBM — not which ticker “wins.” For the memory roles map, see who makes HBM; for the attach gate, see what CoWoS is.

Who makes AI chips?

Who makes AI chips splits into four roles. Accelerator designers own the GPU or ASIC architecture. Foundries fabricate the logic wafers on advanced nodes. Advanced-packaging partners attach those dies beside HBM. Memory makers build the HBM cubes. Missing any one role leaves the rack waiting — even when CapEx is approved.

Who designs the accelerator?

Accelerator designers set the architecture and software stack. NVIDIA announced the Blackwell platform — including the GB200 Grace Blackwell Superchip and GB200 NVL72 rack-scale system — on 18 March 2024 (NVIDIA Newsroom). On 18 March 2025 it announced Blackwell Ultra with the GB300 NVL72 and HGX B300 (NVIDIA Newsroom) — company-reported product claims.

AMD unveiled the Instinct MI350 Series (MI350X / MI355X) on 12 June 2025 at Advancing AI (AMD IR). Hyperscaler custom ASICs sit in the same designer role: Google’s Trillium sixth-generation TPU reached general availability on 11 December 2024 (Google Cloud Blog). Those dates show the role, not a ranking — generations move; the job stays design.

Who fabricates the logic wafers?

Foundries turn the design into silicon. Leading AI GPUs and many custom ASICs run on TSMC advanced nodes, then move into advanced packaging. That is a foundry role — wafer fabrication — separate from designing the accelerator or building the DRAM stack. See foundry and advanced packaging.

When CapEx orders bind scarce advanced-node capacity, cash sticks at the foundry step even if designs are ready. Samsung Foundry also fabricates advanced logic for some customers — labelled by product, not as a share ranking.

Who attaches logic to HBM?

An AI accelerator only becomes useful when logic sits beside HBM on an advanced package. TSMC’s CoWoS family places SoCs and HBM stacks on an interposer or local-silicon-bridge package; CoWoS-L has been in volume production since 2024 (TSMC CoWoS page). That is packaging attach — not DRAM fabrication and not GPU design. For the memory side of the same bind, see what HBM is.

TrendForce (18 Sep 2026) keeps CoWoS-L as the mainstream AI packaging path through 2028 on maturity and yield versus EMIB-T — reported research, not a TSMC filing. When package slots are short, cash sticks at attach capacity; designers and memory makers can still wait.

Who supplies the HBM stacks?

HBM cubes come from DRAM stack makers. SK hynix announced volume production of 12-layer HBM3E at 36 GB on 26 September 2024 (SK hynix Newsroom). Micron, on 5 September 2024, said it was shipping production-capable HBM3E 12-high 36 GB units with more than 1.2 TB/s, and noted CoWoS / OSAT collaboration. Full memory roles map: Who Makes HBM.

Who gets paid — and where is the stuck step?

On the Semiconductors layer, who gets paid tracks which role clears first when AI CapEx orders arrive. Designers clear on wins; foundries clear when advanced wafers bind; packaging clears when CoWoS-class slots bind; HBM makers clear when scarce cubes are allocated. The stuck step is usually foundry plus packaging plus HBM together — orders can rise while installs wait.

Korea markets door where memory allocation bites: Korea HBM — who gets paid when AI memory stays scarce. Wire on the packaging clock: CoWoS-L stays the packaging path through 2028. Analysis on where the bind moves next: If packaging catches up, where does the stuck step move?.

Common misconceptions

• People assume “who makes AI chips” means one company. Actually four roles share the chain: designers, foundries, packaging attach, and HBM makers. Missing any one role leaves the accelerator waiting.
• People assume the designer also fabricates the wafer and the HBM cube. Actually most leading AI GPUs are designed by one firm, fabricated at a foundry, packaged with HBM from memory makers. Roles are separate even when brands appear on one board.
• People treat a market-share table as a tip sheet. Actually this page maps roles and stuck steps. Share prints from trade press are labelled reported and are not buy/sell advice.
• People assume packaging is just assembly after the “real” chip is done. Actually CoWoS-class attach is often the short clock. TrendForce (18 Sep 2026) keeps CoWoS-L mainstream through 2028 — reported — because package size and HBM count keep rising.

FAQ

Related terms

• Who Makes HBM — roles map for the memory stack chain.
• HBM — what high-bandwidth memory is.
• CoWoS — the packaging attach that sits next to HBM.
• Foundry and advanced packaging — wafer fab and package attach as one money chain.

Markets and stack doors

Layer: semiconductors. Markets: Korea HBM memory.

Further reading

Wire: CoWoS-L through 2028 — packaging still binds. Analysis: where the stuck step moves if packaging catches up.

Get the Wire — short notes when foundry, packaging, or HBM clocks move.

Sources