What Is SoIC? Why Stacking Chips Still Leaves HBM Beside the GPU

EXPLAINED · Mechanism · Last reviewed: 26 Oct 2026 · Next review: after TSMC reports fourth-quarter 2026 results

SoIC, or System on Integrated Chips, is TSMC’s wafer-level way of stacking finished chips on top of one another so they behave like a single piece of silicon. The stacked block can then be dropped into a larger package such as CoWoS, which is how high-bandwidth memory still sits beside the compute die rather than on it.

In short. SoIC is TSMC’s 3D stacking service: known-good dies bonded at a pitch that starts below 10 micrometres, then sent on to CoWoS, InFO or a conventional package. 3-nanometre SoIC stacking entered volume production in 2025. CoWoS is still growing — TSMC is producing 5.5-reticle interposers, with a 14-reticle version (about 10 compute dies and 20 HBM stacks) slated for 2028. Our read: SoIC adds a third dimension of logic. It does not yet move AI memory off the interposer. Heat, not the copper join, is the stuck step for putting HBM on the GPU.

Why an investor cares: every extra millimetre of an AI package is now a fight between compute, memory and cooling. Our hybrid bonding explainer covers the copper join; our CoWoS explainer covers the interposer that still carries HBM. This page is the vertical step between them.

What is SoIC?

SoIC is TSMC’s name for a wafer-level 3D stacking platform. A designer partitions a system into chiplets — compute, cache, I/O, sometimes a photonic engine — and TSMC bonds known-good dies of different sizes, functions and process nodes into one SoC-like chip. From the outside the result looks like a single die. Inside it is a stack.

Three properties matter for cash. Heterogeneous integration: the top and bottom dies need not share a node or a size, which is how a cache die lands on a CPU or a compute die lands on an I/O die. Pitch: TSMC says the bond pitch starts from the sub-10-micrometre rule, denser and lower-power than a solder microbump. And the stack is not the finished AI package. TSMC is explicit that SoIC chips can be assembled afterwards with CoWoS or TSMC-SoW. SoIC is the frontend vertical step; CoWoS is the backend lateral step. An AI GPU can, and today does, use both.

SoIC-X is the wafer-on-wafer flavour, for high-yielding nodes and matched die sizes. Gen-2 is in development for N2 and beyond; TSMC’s COUPE photonic engine uses the same 3D family. Our silicon photonics explainer covers the laser that still sits off the silicon.

How does SoIC work?

The sequence is closer to a front-end wafer line than to a back-end assembly house. Completed wafers get a bond-pad layer. Copper pads and the surrounding dielectric are polished flat, plasma-activated, and fused under heat and pressure — die-to-wafer or wafer-to-wafer. Through-silicon vias carry signals through the thinned die. The stack is tested again and sent to whatever package sits around it.

That join is hybrid bonding. SoIC is not a different physics. It is TSMC’s manufacturing wrapper: known-good-die handling, pitch scaling, TSVs, and a promise that the stacked chip can drop into CoWoS or InFO as if it were one SoC.

The production example of logic-on-logic is AMD’s 3D work with TSMC. In May 2021 AMD said it had pioneered, with TSMC, a hybrid-bond 3D chiplet with more than 15 times the interconnect density of then-existing 3D packaging. The first product was a vertical cache on a Ryzen processor. Instinct MI300 took the same idea into AI: up to eight accelerator dies stacked on four I/O dies, with eight HBM stacks still sitting beside them. AMD’s CDNA 3 white paper puts the compute dies on TSMC 5-nanometre and the I/O dies on 6-nanometre. MI300X carries 192 GB of HBM3 at 5.3 TB/s peak — all of it around the stack, not on top of it.

Simplified. Company examples are the firms named in the sources, not a ranking.

How is SoIC different from CoWoS?

Height versus width. SoIC stacks; CoWoS spreads. TSMC’s HPC platform page calls SoIC the frontend 3D stacking technology and CoWoS the backend package that enlarges the envelope so more compute and more HBM fit in one module. CoWoS-S, CoWoS-L and CoWoS-R are the flavours; the bind is reticle size, the area a lithography tool can pattern in one shot.

That lateral clock is still running. In April 2026 TSMC said it is now producing 5.5-reticle CoWoS, after 2025 certification. A 14-reticle CoWoS, about 10 large compute dies and 20 HBM stacks, is slated for 2028, then beyond 14 reticles in 2029. The same release puts A14-to-A14 SoIC in production in 2029, at 1.8 times the die-to-die I/O density of N2-on-N2 SoIC.

Our arithmetic, illustration not forecast: 20 HBM stacks on 14-reticle CoWoS is 2.5 times the eight stacks on MI300X. TSMC is adding more beside even as it sells more on top. The shorthand for using both is 3.5D. If SoIC were going to retire CoWoS, TSMC would not be stretching the interposer toward 14 reticles.

Why does it bind?

Two binds, two clocks. The logic-on-logic join is in volume: TSMC says 3-nanometre SoIC stacking entered volume production in 2025, and AMD has shipped 3D V-Cache for years. Hybrid bonding for logic is no longer a lab trick.

The memory-on-logic join is not. An AI GPU is one of the hottest objects in a data centre; DRAM on top of it blankets the heat path. At a 21 October 2026 technology webinar Micron showed a vertical-HBM roadmap aimed at 2028 volume, three generations through 2030, sitting alongside ordinary HBM in many systems. Micron’s HBM page still describes today’s stacks as DRAM on a base die with TSVs and microbumps. HBM4 36 GB 12-high is in high-volume production at more than 2.8 TB/s per stack — beside the GPU, not on it.

Our hybrid bonding explainer is the sister clock: HBM4 still ships on microbumps. Our Besi Wire is what that looks like in tool orders. SoIC can stack a cache or I/O die today; stacking a full HBM cube onto a 1,000-watt-class accelerator is a different cooling problem. Micron lists advanced thermals as a condition of the 2028 product and has not named a launch customer.

TSMC’s 2029 A14-to-A14 SoIC date is the logic clock. Micron’s 2028 vertical-HBM date is the memory clock. CoWoS at 14 reticles in 2028 is the lateral clock that fills the gap if either vertical date slips.

Who gets paid — and where is the stuck step?

Four groups of cash.

TSMC is paid twice: once for the SoIC stack, once for the CoWoS (or InFO, or SoW) that wraps it. That is 3DFabric. The foundry that makes the dies also sells the vertical join and the lateral interposer. SoIC is an extra process step on the same campus, not a second-vendor bake-off.

Bonding-tool makers are paid as SoIC, and later memory-on-logic, move from development to wafers. The volume that pays them today is logic stacking. HBM4 still uses bumps. Our read: a jump in hybrid-bonding tool shipments is a SoIC, 3D-cache or custom-base-die signal before it is an HBM-on-GPU signal.

Memory makers are still paid for stacks around the edge. SK hynix, Samsung and Micron get the HBM that CoWoS is being stretched to hold — 20 stacks on the 2028 14-reticle outline. Vertical HBM, if it arrives, is extra content on the same GPU, not a substitute. Micron said the on-top product sits alongside the beside product.

Chip designers are paid for the accelerator. AMD already ships the 3.5D pattern. Nvidia’s current AI GPUs are CoWoS-and-HBM machines; TSMC’s SoIC roadmap through A14 is the option for more compute, or a photonic engine, in the same footprint without waiting for memory-on-logic.

The stuck step is heat on the memory path, and CoWoS size on the path that still works. SoIC is not the scarce step for AI GPUs in 2026; the package that places HBM beside the die still is. TSMC’s 2026–2029 disclosures spend more sentences on reticle multiples than on SoIC wafer starts. We have no primary SoIC capacity figure, and we will not borrow one from a secondhand note.

Our arithmetic on the lateral clock, TSMC’s own outline: eight HBM stacks on MI300X to about 20 on 14-reticle CoWoS is a 12-stack increase per module. TSMC is still multiplying the beside number.

What would change the view?

• Memory-on-logic names a customer. A GPU or ASIC that ships with DRAM on the compute die turns 2028 into a design-win, and SoIC-class bonding for memory becomes the bind instead of CoWoS reticle size.
• CoWoS 14-reticle slips. Designers would wait, or pull more bandwidth into a vertical stack sooner.
• SoIC A14-to-A14 slips past 2029. More of the AI package’s scaling would stay on CoWoS and on larger HBM stacks.

Common misconceptions

• People assume SoIC replaces CoWoS. Actually TSMC sells them as a pair. SoIC makes a taller chip; CoWoS makes a wider module that still holds HBM.
• People assume SoIC is hybrid bonding. Actually hybrid bonding is the join. SoIC is TSMC’s process and service that uses that join, plus known-good-die flow and TSVs, and then hands the stack to a package.
• People assume HBM already sits on the GPU. Actually production AI packages still place HBM beside the compute die. Micron’s on-top product is a 2028 target, not a 2026 shipment, and Micron says it would coexist with ordinary HBM.

FAQ

What is SoIC?
SoIC, or System on Integrated Chips, is TSMC’s wafer-level 3D stacking platform. It bonds known-good dies on top of one another at a pitch that starts below 10 micrometres, so the stacked chips look like one SoC from the outside and can then be placed into a CoWoS or InFO package.

How is SoIC different from CoWoS?
SoIC stacks chips vertically. CoWoS places chips side by side on an interposer. TSMC calls SoIC a frontend 3D stacking service and CoWoS a backend packaging service; an AI accelerator can use both, with compute dies stacked by SoIC and HBM still sitting beside them on CoWoS.

How is SoIC different from hybrid bonding?
Hybrid bonding is the copper-to-copper join. SoIC is TSMC’s process that uses that join, plus through-silicon vias and known-good-die flow, to make a 3D stack as a manufacturing service.

Why isn't HBM stacked on the GPU yet?
Because a GPU is hot, and a memory stack on top of it blocks the cooling path. Micron has a vertical-HBM roadmap aimed at 2028, and says it would sit alongside ordinary HBM rather than replace it. Until then, HBM still sits beside the compute die on CoWoS.

Is this a list of stocks to buy or sell?
No. This page explains how SoIC works and where the money goes. It does not rank companies or give buy or sell calls. Not investment advice. Do your own research.

Related: hybrid bonding; CoWoS; HBM; chiplets; interposers; silicon photonics.

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How we check this

Figures come from TSMC technology pages and the 22 April 2026 North America Technology Symposium release, AMD’s 2021 3D-chiplet announcement and CDNA 3 / MI300 materials, Micron’s HBM product page and its 21 October 2026 webinar as covered in our Wire. The 2.5-times and 12-stack multiples are our arithmetic, shown on the page. We do not use secondhand SoIC wafer-start estimates. Where we interpret, it is labelled “our read”. Not investment advice. Do your own research.

Last reviewed: 26 Oct 2026 · Next review: after TSMC reports fourth-quarter 2026 results

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References

1. TSMC — TSMC-SoIC (3DFabric technology page) — wafer-level 3D stacking; sub-10µm pitch; 3nm stacking in volume from 2025; then CoWoS or SoW
2. TSMC — HPC Platform, TSMC 3DFabric — SoIC as frontend 3D stacking; CoWoS as backend; 5.5×-reticle CoWoS certified in 2025, volume production in 2026
3. TSMC — Debuts A13 Technology at 2026 North America Technology Symposium (22 Apr 2026) — producing 5.5-reticle CoWoS; 14-reticle CoWoS (~10 compute dies, 20 HBM) for 2028; A14-to-A14 SoIC for 2029 at 1.8× I/O density vs N2-on-N2; COUPE-on-substrate in 2026
4. AMD — COMPUTEX 2021, 3D chiplet technology with TSMC (31 May 2021) — hybrid-bond 3D chiplets pioneered with TSMC; >15× interconnect density vs then-existing 3D; >200× vs 2D chiplets; first product a 3D vertical cache
5. AMD — CDNA 3 architecture white paper — up to eight vertically stacked accelerator dies and four I/O dies, plus eight HBM stacks; XCDs on TSMC 5nm, IODs on TSMC 6nm
6. AMD — Instinct MI300 Series availability (6 Dec 2023) — MI300X 192 GB HBM3, 5.3 TB/s peak, 3D packaging
7. Micron — High-bandwidth memory product page — HBM4 36 GB 12-high in high-volume production; >2.8 TB/s per stack; HBM described as DRAM dies on a base die with TSVs and microbumps
8. Micron — Technology webinar, 21 Oct 2026 (announcement, 19 Oct 2026) — Scott DeBoer on DRAM, HBM and NAND; webcast at investors.micron.com
9. Second Order — Micron vertical HBM on top of AI chips by 2028 (25 Oct 2026) — 2028 volume target, three generations through 2030, to sit alongside ordinary HBM; heat and bonding as the bind
10. Second Order — Besi orders as HBM still uses bumps (22 Oct 2026) — HBM tool demand still from microbump flows, not hybrid bonding

S

Sean

Writes Second Order by TKN — a plain-English map of AI infrastructure and semiconductors. Focus: who gets paid, where money sticks, and which step is stuck.

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