What Does Advantest Do? The Chip Tester Model

STACK · Semiconductors · Status: Tightening · Last reviewed: 31 Oct 2026

Advantest is a Japanese company that makes automated test equipment, the machines that check whether a chip works before it is shipped. Chipmakers, foundries and test houses buy its testers to check AI processors, CPUs and memory, then pay it again for interface boards, upgrades and service.

Why an investor cares: every AI chip has to pass test before it can be sold, and each new generation spends longer on the tester than the last. Advantest sits at that gate for most of the industry’s processors. If you want the whole test chain, from tester makers to test houses, start with our guide to who tests AI chips. This page is about the company that makes most of the machines.

Numbers that matter

Company and analyst figures are listed at the end of the page. The quarterly rise is our arithmetic from ¥367.5bn to ¥477.7bn.

What does Advantest actually do?

It builds the machines that decide whether a chip ships. A tester sends signals into a chip, reads what comes back and compares it with what a good chip should do, pin by pin and at full speed. A chip is tested at least twice: once while it is still part of a wafer, through a probe card that touches each die, and again after it has been packaged, often followed by burn-in and system-level test.

Advantest sells into both steps. Its main products are the V93000, a platform for testing system-on-chip devices such as GPUs, custom AI chips, CPUs and network chips, and a range of memory testers for DRAM and flash. Around those it sells test handlers that move chips in and out, device interfaces that connect each chip design to the tester, and system-level test machines.

The company was founded in 1954 as Takeda Riken Industries, a maker of electronic measuring instruments, and launched Japan’s first semiconductor test systems in 1972. Its biggest step came in 2011, when it bought Verigy, then a major rival in chip test. That deal brought the V93000, first launched in 1999, which is now the base of its AI business.

Almost none of its sales are at home. In the six months to September 2026, 99.4% of sales went to customers outside Japan. On Advantest’s regional chart, more than half of July–September sales, ¥261.3 billion of ¥477.7 billion, shipped to Taiwan, where most AI processors are made and packaged. Our guide to who makes advanced packaging covers the step just before test.

How does Advantest make money?

Mostly by selling machines. In July–September 2026 test systems brought in ¥436.7 billion of its ¥477.7 billion sales. SoC testers were ¥353.3 billion of that and memory testers ¥53.4 billion; the rest, about ¥30 billion on our arithmetic, came from handlers, system-level testers and device interfaces. Services and others added ¥41.1 billion, from support contracts on the installed base and consumables such as test interface boards.

The margins are unusually high for a machine maker. Gross margin passed 70% in the quarter, at 71.1%, and operating margin was 55.9%, because the most complex and most expensive testers, the ones used on AI chips, made up more of the mix. Advantest expects a gross margin of about 68% for the full year and an operating margin of 51.9%.

For the year to March 2027 it now expects sales of ¥1,863.0 billion and operating income of ¥967.0 billion, up from ¥1,714.0 billion and ¥846.0 billion in its July forecast. Second-half sales are expected to be about 20% above the first half. The yen helps: Advantest says each one-yen fall against the dollar adds about ¥5.8 billion to annual operating income.

The chart shows the shape of the business. SoC tester sales are on course to roughly triple in two years, on our arithmetic, and the October forecast is ¥131.5 billion above the July one. Advantest said that increase did not come from a bigger market forecast, which it left unchanged. It came from building and shipping more machines than it had planned.

Why is demand still rising?

Two forces stack on top of each other: more AI chips, and more test time per chip. Advantest put it plainly on 28 October: tester demand is driven by rising chip volumes, along with more test content and more test insertions with each new generation.

The test time effect is large. Nomura estimates, as reported by TrendForce in October, that NVIDIA’s Blackwell takes about four times as long as Hopper in final test and Rubin about seven times as long. Nomura also estimates that testing’s share of a GPU’s manufacturing cost rises from 1.9% for Hopper to 2.5% for Blackwell and 3.3% for Rubin. Our arithmetic: if a Rubin chip ties up a tester seven times as long, the same tester handles about one-seventh as many of them in an hour.

The demand is also spreading. Advantest said the biggest single reason for raising its SoC tester forecast was CPUs, as AI agents push up the number of server CPUs and the ratio of CPUs to GPUs in inference. That sits on top of GPUs and custom AI chips, the subject of our guide to who makes custom AI chips. Further out, it expects testers for co-packaged optics, where light and electronics share a package, to double or triple each year towards a market of about $1 billion.

Advantest sizes the SoC tester market at about $11.5 billion in 2026 and the memory tester market at $2.5 billion to $3.0 billion, against about $6.0 billion for both together in 2024. It says the tester market has grown by about 50% a year on average over the past few years, and it does not yet see that slowing. Those are its estimates, and it will give a number for 2027 in January.

Who gets paid first?

• Advantest. It is paid when each tester ships, at a gross margin above 70%, and customers are paying ahead: advance receipts rose by ¥44.2 billion in the six months to September. Each tester sold then earns service fees and interface board sales for years.
• Its parts suppliers. Every SoC and memory tester uses a lot of DRAM, and Advantest says higher DRAM prices are a major reason its second-half margin will dip. The memory makers are paid before Advantest’s margin is.
• The test houses. Companies such as KYEC, ASE and Sigurd buy the testers and sell the hours. TrendForce reported in October that Sigurd’s customers are signing capacity deals of more than a year and that Sigurd has started raising prices.
• The chip designers, who pay for all of it. NVIDIA and the custom chip designers carry the bill, and on Nomura’s estimate test takes a growing share of what each GPU costs to make.

Our analysis of the CoWoS stuck step shows the same pattern one step earlier in the line: when a step is short, the owner of the scarce machine or slot sets the terms.

What limits it?

Its own factories. Advantest can now build more than 5,000 SoC testers a year. Its plan had been to reach 10,000 a year by the end of the 2028 fiscal year, in March 2029. On 28 October it said that date must come forward significantly and that it is highly confident it can do so, but it gave no new date. A further doubling, to 20,000 a year, is under internal discussion.

To get there it uses a hybrid model: its own plants for the hardest work, and outside electronics manufacturers for volume. That spreads the risk, but it also means Advantest’s output depends on how fast partners and parts suppliers can grow with it. It will explain its supply chain plan at an investor session on 12 November.

The second limit is memory. Advantest said memory supply is tight across the industry and that it is not immune. DRAM makers have shifted output from older DRAM towards HBM and server memory, the subject of our HBM explainer, and its customers know memory has to be made available for testers to be delivered. Our read: the AI build-out is now competing with itself, because the memory that goes into AI servers is also needed inside the machines that test AI chips.

The third limit is the rest of the line. Testers only earn their keep when chips reach them. Advantest expects semiconductor and advanced packaging supply to stay short of demand through 2027. TrendForce, citing Commercial Times, reported that chip equipment lead times have stretched to six to eight months from three to six. A tester that ships before the packaging line is ready waits.

Our read on the stuck step: for the next year it is Advantest’s ability to build testers, not customers’ willingness to buy them. That is why the forecast rose on capacity rather than on a bigger market, and why we mark the status Tightening.

Who else does this?

Teradyne of the US is the other large tester maker. In the quarter to 27 September 2026 it reported $1,306 million of revenue, of which $1,072 million came from semiconductor test, with record memory test sales. Advantest’s test system sales of ¥436.7 billion in July–September were about $2.7 billion at its average rate of ¥161 to the dollar, our conversion, so roughly two and a half times Teradyne’s semiconductor test revenue.

Downstream, NVIDIA expects its total testing capacity to double from 2026 to 2027 and has given KYEC a $1.1 billion advance to build US test sites. Those sites need testers, and Advantest estimates it holds about two-thirds of the SoC tester market. Upstream in the fab, the toolmakers on this layer, such as KLA and Tokyo Electron, sell into wafer making; Advantest sells into the step after it. Our guide to who makes wafer fab equipment covers that earlier step.

What would change this view?

• Easing: Advantest names a near date for 10,000 testers a year, or DRAM prices fall enough to lift its second-half margin back above the first half’s.
• Tightening further: component shortages slow shipments in the January quarter, or the packaging lines before test run late and push tester deliveries back.
• A shift in share: Teradyne winning a large AI processor as a second supplier would show whether the 66% share can keep rising towards 70%.

Practical takeaways

Read Advantest as a toll on the last gate before an AI chip ships. Its growth now depends on how many testers it can build and how much memory it can get, not on whether customers want them. The next dates are its supply chain session on 12 November and its third-quarter results in January 2027, when it has said it may give the 2027 market outlook and a date for 10,000 testers. Our Wire on CoWoS prices and chip testing tracks the step just before it.

FAQ

Keep reading on the map

Layer: Semiconductors. Also on the layer: TSMC, SK Hynix and ASML. Explained: chiplets. Analysis: the ASE packaging stuck step.

Get the Wire — short daily notes when testers, packaging lines and memory supply move.

Not investment advice. Do your own research.

References