What Does Samsung's Price Assume About the Memory Wafer-Pool Stuck Step?

ANALYSIS · MEMBERS CONTINUE · 4 min free / 12 min full · Data as at 30 Sep 2026

Samsung Electronics sits at the memory wafer-pool stuck step — DRAM starts that can become HBM stacks or commodity DRAM, then still need attach before a billed GPU hour. At roughly ₩1.735 trillion (~$1.28 trillion), the question is not whether AI wants HBM — it is what growth, mix, and attach that price already assumes as industry HBM wafer share moves from about 20% toward nearly 30%.

In short

• The question: what is today’s price for Samsung already assuming about the memory / HBM wafer-pool stuck step?
• The answer: Scenario B — Device Solutions memory keeps compounding on HBM4 stacks that clear attach plus commodity DRAM supported by the same wafer pool tightening, while the industry HBM share guide (~20% → nearly 30% of DRAM wafers next year) is a starts bind, not proof those wafers are already paid GPU hours; zHBM / HBM5 stay a co-design roadmap, not near-term cash
• Why: Q2 DS operating profit was ~₩89.2 trillion of a company ₩89.5 trillion print; HBM revenue share jumped to 33% in Q2 (Counterpoint); company guided HBM4 revenue >3× QoQ into Q3 and HBM4 >60% of HBM mix in H2 — all attach-and-ASP clocks, not zHBM shipping
  Behind the wall: three scenarios with the arithmetic · what ~₩1.735T / ~$1.28T implies · six practical takeaways · Members' FAQ
• What would break it: HBM stacks failing to clear attach while wafer starts keep rising — or commodity DRAM never tightens when the mix shifts, while the equity still pays for Scenario B memory earnings
• Nothing here is a recommendation. This is a map of what the price requires, with the working shown

What's in this piece: the numbers that matter · why Samsung sits at the wafer-pool stuck step · what the price implies in one line · members from here · who gets paid · three scenarios, arithmetic shown · our read · what would change the view · practical takeaways · FAQ · sources

The numbers that matter

Chart 1 — Two clocks on one equity. Wafer starts shift to HBM; cash still waits on attach. Sources: CNA/Reuters 29 Sep 2026; Samsung Q2 30 Jul 2026; Counterpoint via SED. Education only.

Why does Samsung sit at the memory wafer-pool stuck step?

The semiconductors layer turns DRAM wafers into stacks, then into packages beside (or someday on) an accelerator. What Is HBM? and Who Makes HBM are the mechanism: cash clears when a customer uses a working GPU and pays for that hour. Wafer starts are not that hour.

Samsung sits where the starts are allocated. On 29 September 2026, Executive Vice President Kim Taewoo said HBM is expected to take nearly 30% of industry DRAM wafer capacity next year, up from about 20% now, and that HBM and standard DRAM compete for the same wafer capacity (reported: Channel NewsAsia, 29 Sep 2026; Reuters via MarketScreener, 29 Sep 2026). The same Tuesday, DRAM development SVP Kim Kyung-ryun laid out HBM4E sampling, HBM5 targets, and zHBM stack-on-processor ambitions at the Herald Business Forum (Herald Business, 29 Sep 2026). Our Wire covered the signal. This piece asks what 005930’s equity price already assumes about the bind.

Distinct from Hanmi at the memory stuck step (bonders every stack needs) and from ASE at packaging (OSAT overflow). Those ask about tools and join capacity. This asks what one memory maker’s market value requires of the wafer-pool → attach path.

The wafer-pool bind is simple once you separate clocks. DRAM fabs start wafers. Those wafers can become standard DRAM dies (phones, PCs, non-HBM servers) or the dies that build tall HBM stacks for AI accelerators. Kim’s reported point is that the industry is pointing roughly ten more percentage points of that shared capacity at HBM next year — and that the two uses compete. Industry estimates carried the same day put Samsung’s own HBM wafer input on a path from about 180,000 wafers a month this year toward about 250,000 in 2027, with the HBM4 family rising toward roughly 80% of Samsung’s HBM shipments (TrendForce / Seoul Economic Daily industry estimates, 29 Sep 2026). That is a starts story. The attach story is separate: HBM dies still need stacking and a 2.5D (or later 3D) join before an accelerator can bill. zHBM, as described in the same-day keynote, would move memory onto the processor — a co-design bind, further from a commodity DRAM invoice.

So the equity question is not “is HBM demand real?” Q2 already answered that with DS operating profit near ₩89 trillion and a Counterpoint HBM revenue share of 33%. The question is what ~₩1.735 trillion already requires of the path from wafer start → cleared stack → commodity tightness — and what it does not require of zHBM.

What does ~₩1.735 trillion (~$1.28 trillion) already assume?

Work backwards from the close. At ₩272,500 on 29 September 2026 (~₩1,735 trillion / ~$1.28 trillion on ~6.57 billion shares), against trailing net income of about ₩135 trillion, the earnings multiple is roughly 13×. Against a crude Q2×4 operating-profit run-rate of about ₩358 trillion (₩89.5T × 4), the OP multiple is about 4.8×. DS alone printed ₩89.2 trillion of OP in one quarter — almost the entire company — on Memory sales near ₩120.8 trillion.

Our read, in one line: the price assumes Scenario B — DS memory keeps compounding on HBM4 stacks that clear attach and on commodity DRAM supported by the same wafer pool tightening (~20% → nearly 30% industry HBM wafer share), while zHBM / HBM5 stay a co-design roadmap that need not contribute near-term cash; wafer starts are not billed hours. The three scenarios and the arithmetic are below.

The free preview ends here.

—— Still to read · ~8 of 12 minutes ——

MEMBERS CONTINUE HERE

• Three scenarios with the arithmetic
• What ~₩1.735T / ~$1.28T requires in wafer mix, HBM attach, and commodity ASP
• Six practical takeaways
• Members' FAQ