What Is a Silicon Wafer? How It’s Made, Who Makes It, and Why Supply Is Tight

EXPLAINED · Mechanism · Last reviewed: 13 Nov 2026 · Next review: after SEMI’s fourth-quarter 2026 wafer shipment count and the wafer makers’ fourth-quarter results

A silicon wafer is a thin, polished disc of single-crystal silicon, up to 300 mm across, on which chips are built.

Why an investor cares: every AI processor and every stack of HBM starts as a blank wafer bought from outside the fab. When those wafers get tight, the chipmaker’s plan waits, and the wafer maker gains pricing power it has not had for years. This page sits under our Semiconductors layer, upstream of everything else on it.

What is a silicon wafer?

A silicon wafer is the blank disc a chip is built on: a slice of one continuous silicon crystal, polished flat enough to print circuits measured in nanometres. A chipmaker, or fab, buys blank wafers, then deposits, prints and etches layer after layer of circuitry on them. At the end, the finished wafer is cut into individual chips.

The disc itself carries no circuits. Its job is to be perfect: one crystal with its atoms in a regular lattice, almost no impurities, and a surface flat and clean to within atoms. Any defect in the wafer becomes a defect in the chips printed on it.

SEMI, the industry association, describes wafers as the substrate on which most semiconductors are made, in diameters of up to 300 mm. What gets built on top is covered in our 2nm chip Explained; how many of those chips survive is in our semiconductor yield Explained.

Second Order summary of SEMI and company product descriptions.

How is a silicon wafer made?

A silicon wafer is made by growing a single crystal, slicing it and polishing the slices. The steps run in a fixed order, and each one has its own specialist equipment.

• 1. Purify. Polysilicon is refined to semiconductor grade, far purer than the material used in solar panels.
• 2. Pull the crystal. The polysilicon is melted in a quartz crucible. A small seed crystal is dipped in and drawn slowly upward while it turns, so the melt freezes onto it as one crystal. This is the Czochralski method. The result is a cylindrical ingot, rounded at the seed end like the one in the photo above.
• 3. Shape and slice. The ingot is ground to an exact diameter and sliced into thin discs with wire saws.
• 4. Lap, etch and polish. The discs are flattened, chemically etched to remove damage, and polished to a mirror finish.
• 5. Grow an epitaxial layer, if needed. For leading-edge logic, a thin layer of extra-pure crystal is grown on the polished surface.
• 6. Clean, inspect and ship. Each wafer is cleaned, measured and sealed in a pod for the fab.
• 7. Qualify. Before a new line or plant can supply a chipmaker, the customer tests its wafers in its own process. GlobalWafers says its new Texas plant is ramping as customer qualifications advance.

The fab that receives the wafer is a different business, with its own clean rooms and tool makers. The wafer maker’s work ends where the fab’s begins.

What sizes do silicon wafers come in?

Silicon wafers come mainly in 300 mm and 200 mm diameters, with smaller sizes for older devices. A 300 mm wafer has about 109.6 square inches of area, 2.25 times a 200 mm wafer, by our arithmetic. More area per wafer means more chips per pass through the fab, which is why every leading-edge plant is built for 300 mm.

Areas are Second Order arithmetic from the diameter. Uses from SEMI, SUMCO and Shin-Etsu commentary.

The two sizes serve different markets, and in 2026 both are tightening for different reasons. SUMCO said 300 mm demand was being driven by advanced logic and memory for AI and data centres, while 200 mm demand was rising for AI-related power devices.

How many silicon wafers does the world use?

The world shipped 3,756 million square inches of silicon wafers in the third quarter of 2026, according to SEMI. That was 13.4% more than a year earlier and 5.1% more than the second quarter. The industry counts by area, not by wafers, so that different diameters can be added together.

If all of that area were 300 mm wafers, it would be about 34.3 million wafers in the quarter, or about 11.4 million a month, by our arithmetic. The real count is higher, because part of the area is in smaller wafers.

The first nine months of 2026 added up to 10,604 million square inches, 11.2% more than the same months of 2025, by our arithmetic. SEMI’s annual forecast, published on 21 October 2026, expects 14,420 million square inches for the full year, up 11.8%, and successive records to 17,034 in 2029. That is about 18% more over three years, or roughly 5.7% a year, by our arithmetic.

Shin-Etsu gave the same picture from inside the market. On 27 October 2026 it said the wafer market rose by a mid-single-digit percentage in the July to September quarter and by just over 10% on a year earlier, with 300 mm wafers following the same pattern.

Why does AI use more silicon wafers?

AI uses more silicon wafers because it needs more chips of every kind, and many of those chips use more silicon per unit of output. SEMI and the wafer makers point to five sources of demand.

• Leading-edge logic. AI processors are built on epitaxial 300 mm wafers. SUMCO said chiplet designs for GPUs and CPUs are lifting logic wafer demand across several process generations, not only the newest.
• Memory, beyond HBM. SEMI’s forecast says memory demand extends from HBM to server DRAM and enterprise NAND, all on polished 300 mm wafers. Our HBM Explained covers why each stack needs so much silicon.
• Bonding and advanced packaging. SEMI said bonding and packaging continued to support demand for 300 mm polished wafers. Silicon is used as carrier wafers and as the interposer under an AI chip, and hybrid bonding stacks wafers on wafers.
• Photonics. GlobalWafers said its output of 12-inch silicon-on-insulator wafers hit a record, with demand for silicon photonics, RF and power uses above its expansion plan. Our silicon photonics Explained covers the optical side.
• Power devices. SEMI said AI demand had broadened to power devices and that AI server power supplies were lifting industrial demand. Siltronic said demand for 200 mm wafers was increasingly strong.

Who makes silicon wafers?

Silicon wafers are made by a small group of specialist companies, not by the chipmakers themselves. The best known are Shin-Etsu Chemical and SUMCO in Japan, GlobalWafers in Taiwan, Siltronic in Germany and SK Siltron in South Korea. Four of them reported results in the past three weeks.

From each company’s results materials listed under References. Not a ranking.

The group is tied together in places. GlobalWafers holds shares in Siltronic, and its own results swing with their market value. Siltronic’s newest 300 mm capacity is in Singapore, and the company said that expansion is how it is supporting AI-driven growth. GlobalWafers has a new plant in Texas, a 12-inch silicon-on-insulator plant in Missouri, a new 12-inch line in Novara, Italy, and plants in Japan.

Their customers are the foundries and memory makers. Our who makes HBM page covers the memory side of that customer list.

How are silicon wafers sold?

Much of the world’s silicon wafer volume is sold under long-term agreements: multi-year contracts that set volumes and prices, sometimes backed by a customer prepayment. The rest is sold on shorter terms, and that is where prices move first.

• Contract prices held. SUMCO said long-term agreement prices were maintained in the third quarter of 2026, and that it would serve extra demand based on existing customer relationships and prices.
• Extra volume costs more. Shin-Etsu said it had asked customers to accept higher prices for additional volumes, and that for some customers increases would apply from October 2026. It is also negotiating with customers that have no long-term agreement.
• Next contracts are opening early. Shin-Etsu said more customers had begun negotiating their next contracts while existing ones were still in force, out of concern about further supply limits.
• Customers pay ahead. GlobalWafers reported NT$21.2 billion of customer prepayments, about US$0.67 billion, or roughly 1.4 times its third-quarter revenue, by our arithmetic. Micron agreed to subscribe to up to US$500 million of a 10-year GlobalWafers convertible bond, alongside a planned 10-year supply agreement.

The logic is the same as a purchase commitment on the buyer’s side: the customer locks in supply for years, and in return the supplier gets visibility and, sometimes, cash up front to build.

Who gets paid?

Our read: the wafer makers are paid first, the customers who signed long contracts are protected, and the buyers without contracts pay the new price.

• Wafer makers, on volume first. Siltronic’s third-quarter sales rose 10.5% on the quarter to €355.4 million, driven by higher wafer area sold; it said price and product mix had only a limited effect. SUMCO’s 300 mm shipments rose sharply. The money so far comes from volume. Price is the next step, starting with extra volume and new contracts.
• Not yet on margin. The makers are still carrying the cost of the last build-out. SUMCO earned an operating profit of ¥2.0 billion on ¥117.5 billion of sales in the third quarter, a 1.7% margin, while its EBITDA margin was 29.8%: depreciation took about 94% of EBITDA, by our arithmetic. Siltronic’s gross profit was −€7.5 million, with about a third of its cost of sales in depreciation.
• Chipmakers with long contracts. They pay the agreed price and get first claim on volume. Shin-Etsu said leading-edge logic wafers are priced more finely by specification, so a richer mix lifts its average price even before any increase.
• Buyers without contracts. They face the price increases first and are served after contract customers.
• Customers funding supply. Micron’s bond and GlobalWafers’ prepayments show the customer paying part of the cost of new capacity in exchange for a place in the queue. Our Analysis on memory sold years ahead follows the same pattern one step downstream.

Where is the stuck step?

Our read: the crystal itself. Wafer demand can rise in a quarter, but new crystal-pulling and polishing capacity takes years to build and then has to be qualified by each customer. Until it is, the only extra supply is what existing lines can squeeze out.

The makers say so in their own words. SUMCO said on 11 November 2026 that 300 mm supply was becoming unable to meet the volumes customers request in the fourth quarter. It added that, at current prices and with costs rising, adding capacity is not economically rational, and would take several years even if it were decided, so supply and demand would tighten further.

Shin-Etsu said it would be able to raise output only to a limited extent in the first half of next year, through brownfield expansion at existing sites, and that greenfield costs have risen considerably. GlobalWafers said high construction costs, long equipment lead times and qualification cycles limit how fast new supply can be added, and that its capacity across all diameters is fully used.

The spending numbers show the same caution. SUMCO spent ¥29.7 billion on capital projects in the first nine months of 2026 against ¥99.2 billion of depreciation, about 30%, by our arithmetic. Siltronic expects capital spending of €180 million to €200 million in 2026 against €480 million to €500 million of depreciation. Both are running well below their depreciation.

Our photomask Explained covers another upstream input with the same shape: few suppliers, long qualification, and no quick fix when demand jumps.

What would change the view?

• Prices move on contracts, not just extra volume. If new long-term agreements reset at higher prices, the makers would have a reason to build, and the stuck step would start to ease in a few years.
• Capacity is announced. A greenfield 300 mm crystal-pulling plant from any major maker would signal that prices now cover the cost. SUMCO and Shin-Etsu both said they were not there yet.
• Demand pauses. Shin-Etsu expects volume to be roughly flat in the October to December quarter, partly because of maintenance shutdowns. A second flat quarter without maintenance would point to softer demand, not tight supply.
• Supply shocks. GlobalWafers’ third-quarter revenue slipped 2.3% on the quarter after a fire on the 8-inch line at its Italian plant, which shows how one site can move a quarter. Another outage would tighten things faster.

The clocks: Shin-Etsu’s price increases for some customers apply from October 2026; its limited brownfield additions arrive in the first half of 2027; contracts running into 2028 and beyond are being negotiated now; and SEMI’s fourth-quarter 2026 count and the makers’ fourth-quarter results will show whether prices, not just volumes, have started to move.

Common misconceptions

• People assume chipmakers make their own wafers. Actually they buy blank wafers from specialist makers such as Shin-Etsu, SUMCO, GlobalWafers, Siltronic and SK Siltron, then build circuits on them.
• People assume “wafers” in fab news are the same thing. Actually fab wafer starts count blank wafers entering a production line. Wafer makers sell the blanks, and the industry measures them by area.
• People assume rising shipments mean rising profits. Actually depreciation from the last build-out still absorbs most of the gain. SUMCO’s third-quarter operating margin was 1.7%.
• People assume more demand quickly brings more supply. Actually new capacity takes years and needs customer qualification, and SUMCO says today’s prices do not yet justify building it.

FAQ

Related: semiconductor yield; photomask; clean room; interposer; hybrid bonding; who makes wafer fab equipment.

Stack doors

Layer: Semiconductors. Markets: Taiwan and Korea. Markets note: Micron’s Idaho build in its annual report.

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